Design of Electro-Optical Cyclic Redundancy Check Encoder Using Lithium Niobate Waveguide for Reliable Communication

This paper applies probabilistic amplitude shaping (PAS) to a cyclic redundancy check (CRC) aided trellis coded modulation (TCM) to achieve the short-blocklength random coding union (RCU) bound. In the transmitter, the equally likely message bits are first encoded by a distribution matcher to generate amplitude symbols with the desired distribution. The binary representations of the distribution matcher outputs are then encoded by a CRC code. Finally, the CRC-encoded bits are encoded and modulated by Ungerboeck’s TCM scheme, which consists of a systematic $\frac{{{k_0}}}{{{k_0} + 1}}$ tail-biting convolutional code and a mapping function that maps coded bits to channel signals with capacity-achieving distribution. This paper proves that, for the proposed transmitter, the CRC bits have uniform distribution and that the channel inputs have symmetric distribution. In the receiver, the serial list Viterbi decoding (S-LVD) is used to estimate the information bits. Simulation results show that, for the proposed CRC-TCM-PAS system with 87 input bits and 65-67 8-AM coded output symbols, the decoding performance under additive white Gaussian noise channel achieves the RCU bound with properly designed CRC and convolutional codes.

On the cyclic redundancy-check codes with 8-bit redundancy

As Cyclic Redundancy Check (CRC) codes offer the advantages of low power transmission and variable payload length, they have found applications in IoT standards like IEEE 802.15.4 and Bluetooth low energy (BLE). Despite having redundant bits, CRC codes are merely used as error-detecting codes due to the unavailability of a suitable decoder. Several efforts have been made to design a decoder for CRC to use as error-correcting code. The recently proposed GRAND algorithm serves as an error-correcting algorithm for CRC but has huge complexity. In this paper, a low complexity hard decision decoder is proposed for CRC with $g(x)=1+x^{5}+x^{12}+x^{16}$ which is used in IEEE 802.15.4 for IoT applications. The proposed decoder utilizes channel state information (CSI) for decoding in a Rayleigh fading channel and attained fourth-order diversity with very low complexity. The proposed decoder is especially effective at short block lengths; hence it serves as a sound decoder catering to IoT and URLLC services.

Cyclic Redundancy Check (CRC) is a well-established coding method for error detection and is part of several industrial standards for data transmission and storage. If a second CRC is used on top of an existing standard CRC to provide additional reliability, we call this an embedded CRC. The performance of such CRC combinations has been considered only recently and is not yet well understood. In this paper we propose a sieving method, which can be used to find the best embedded CRC for a given standard CRC, and apply the method to common industry standards for field buses.

In this paper, a new list decoding algorithm for tail-biting convolutional codes (TBCCs) with a cyclic redundancy check (CRC) is proposed, where the CRC is considered as a concatenated outer code. The main idea of the proposed algorithm is to modify the list decoding procedure of the TBCC by using the CRC. Two algorithms are proposed for the list decoding of the TBCC with the CRC. The first proposed algorithm is a new initial state estimating algorithm using re-encoded CRC bits and having the low computational complexity. The other proposed algorithm is a modified list Viterbi algorithm, where trellis paths are fixed by re-encoded CRC bits and some CRC bits are used for the error correction. For the TBCC concatenated with the CRC code defined in the long-term evolution standard, the proposed decoding scheme by partially using CRC bits outperforms the conventional list decoding algorithms for the list size $L=4$ even though the proposed algorithm has the lower decoding complexity.

In this paper, the SWAP gate is realized using the electro-optic (EO) phenomenon in the Mach-Zehnder Interferometer (MZI). In the structuring of the SWAP gate, two MZI is being used, and output is obtained from the bar port of both MZI. The SWAP gate output is obtained from MATLAB by using the mathematical description of MZI. The proposed layout of the SWAP gate is designed using titanium diffused lithium niobate (Ti:LiNb03) waveguide and simulated using the beam propagation method (BPM) at 1.33 μm wavelength.

Cyclic redundancy check (CRC) bits that are conventionally used for error detection have recently found a new application in universal mobile telecommunications system standard for message length detection of variable-length message communications. It was anticipated that the CRC bits, when they are coworked with the inner convolutional code, can be used to detect the receiver-unaware of the message length-without much degradation in their error detection capability. This is unfortunately not true when the offset or difference between the wrong detected length and the true length is small. Two improvements, i.e., the DoCoMo's reverse CRC method and the flip CRC method, were accordingly proposed. In this paper, we revisited the flip CRC modification by considering the impact of joint decoding of the CRC code and the convolutional code. By generalizing the condition for the selection of the flip polynomials, we found that under error-free transmission, the range of the length offsets, at which the false length probability conditioning on the true message length can be made exactly zero (and hence, is minimized), can be extended from to , where and are, respectively, the number of the CRC bits and the memory order of the convolutional code. In addition, an upper bound and a lower bound for the overall false length probability with respect to a uniform pick of the true message length over a candidate message length set are derived. It is then confirmed numerically that the two bounds almost coincide for moderate value. Simulations show that the false length probability obtained analytically under error-free transmission assumption only mildly degrades for moderate-to-high SNRs. Interestingly, we also found that the system block error rate of the flip CRC method can be well approximated by the performance curve of the adopted convolutional code up to a certain SNR, and approach an error floor determined well by the previously derived false length probability bounds beyond this SNR, thereby facilitating the selection of the system parameters, such as the number of CRC bits and the memory order of the convolutional code.

Clock accuracy is critical to the performance of UHF (Ultra High Frequency) RFID (Radio Frequency Identification) tag, especially for the encoder in baseband. To reduce the bit error rate of the responded data from tag, a novel clock strategy is proposed in this paper, which generates a high accuracy clock for the encoder by counting the preamble of the commands from reader. Moreover, for reducing the chip area and the power consumption, a novel CRC (Cyclic Redundancy Check) generator is designed, which reuses the resource and fulfills a no-gap-link between the responded data and CRC code. The baseband of tag is implemented in a 0.18μm CMOS process and its area is 75479μm.Simulation results show that the frequency variation of the clock is within a reasonable range. 

The method of cyclic redundancy check (CRC) was been used in the process of RFID communication adopts to ensure that the data was transfer correctly. The principle of CRC was been introduced. The design method about 16-bit CRC code was been gotten through the hardware circuit and hardware description language. And it was compatible with the serial and parallel two kinds of data streams. At the same time it was been verified correctly in RFID communication system. And the results are verified in the specified clock frequency in xc2vp4-6fg256 device in FPGA Xilinx kit using VI-IDL in RTL level. It with strong portability could extend to all CRC system.

In this paper, we investigate interleaved cyclic redundancy check (CRC) code. The interleaved CRC can be obtained by merging independent small message blocks into one large block (merged interleaving) or by dividing the original message block into independent small sub blocks (divided interleaving) and then by alternatively dividing the resulting message block(s) using same generator polynomial. The interleaved CRC increases both the detection span and the detectable error patterns. New applications of the interleaved CRC as the error detection scheme or stopping criteria in interleaved error correction coding and iterative decoding schemes are proposed. Since each individual codeword of interleaved CRC code is mutually independent, it is possible to generate CRC in interleaved manner and to check CRC in parallel manner.

Cyclic Redundancy Check codes (CRC) are widely used in data communication and storage devices for detecting burst errors. In applications requiring high-speed data transmission, multiple bits of an CRC are computed in parallel. Traditional methods for constructing an Linear Feedback Shift Register (LFSR) generating k bits of an CRC in parallel are based on computing kth power of the connection matrix of the LFSR. We propose an alternative method which is based on computing kth power of the transition relation of the LFSR. We use Binary Decision Diagrams (BDDs) for representing the transition relation and we keep the transition relation partitioned. This allows us to bound the size of BDDs by O(n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), where n is the size of the LFSR. Our experimental results show that the presented algorithm asymptotically improves the complexity of previous approaches.

The nonlinear optical waveguide is one of the essential components of modern photonic integrated circuits. A high-quality lithium niobate (LN) waveguide has recently become available due to advances in thin-film LN materials and the associated fabrication techniques. In the past few years, LN waveguide-based nonlinear photonic devices have been intensively investigated due to their ultra-low loss and large index-contrast features. Here we review the recent progress in LN waveguide-based nonlinear photonics devices, including both passive and active components. We believe that LN-based nonlinear photonic devices will make a profound impact on modern photonic society.

A novel 0.98/1.55 μm dichroic coupler with high-extinction ratio and low insertion loss has been designed and implemented on LiNbO3 for Erbium-doped fiber amplifier applications. The design of dichroic coupler is based on a modified directional coupler structure with a single bend in each channel. Beam propagation method is used to analyze the coupler performance to get the optimal parameters for device design, such as channel width, titanium thickness, channel gap, and interaction length. Samples with the signal coupling ratio as high as 100% and pumping power ratio as high as 95% have been obtained.

In this paper, we provide an analysis of the performance of concatenation of polar codes with outer cyclic redundancy check (CRC) codes, separated by an interleaver, in the short and moderate block length regimes. The analysis addresses maximum likelihood decoding as a proxy to the code performance under successive cancellation list decoding. The analysis is carried out by introducing the concatenated polar code (CPC) ensembles, whose distance properties can be analyzed (for sufficiently short block lengths) by means of the uniform interleaver approach. At moderate block lengths, we resort to the Monte Carlo simulations. Results show that if the inner polar code possesses a low minimum distance and the outer CRC code has a sufficiently large amount of redundancy, then the choice of the outer code generator polynomial and the interleaver may yield to a large variability in the performance of the resulting CPC.

An energy efficient authentication scheme for cluster-based wireless IoT sensor networks