Design of high efficiency monolithic CMOS Class-E power amplifier for WLAN application

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This paper presents the design insights for the implementation of a monolithic radio frequency (RF) Class-E power amplifier for WLAN applications. The proposed high efficiency monolithic CMOS class-E power amplifier showcases the effective RF performance enhancement which is composed of two-stage structure and adopts a differential cascode topology with self-biased technique. The differential stage using differential cascode structure with current mirror can improve power gain and enhance the driving ability of switch stage. The switch stage utilizing self-biased technique and inserting a series LC networks on drain node of switch transistor considerable improve efficiency. This presented monolithic PA is simulated by Advanced Design System (ADS), designed and fabricated in the 0.18-μ RF CMOS process. The entire monolithic class-E PA system delivers maximum output power of 24.3dBm and the power added efficiency is 67.4% with 1.2 V supply. By optimizing element parameters, input and output have good matching features.