Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes

This paper presents an optimization method of area and power for static memory elements by using multi-mode power gating (MMPG) scheme. A 2-transistor MMPG scheme replaces the usual 5-transistor one to effectively reduce on chip area overhead and leakage power, simultaneously combining trimming circuits (TC) to guarantee the safety of data retention. When applying the proposed approach into clean/dirty-cache (CD-cache), we can reduce area overhead and leakage power consumption. The simulation results show that the area overhead of SRAM with the proposed approach is reduced from 33.4% to 21.8% compared to that of SRAM with usual MMPG. On the other hand, leakage power is reduced by 12.35% compared to SRAM with usual MMPG and by 86.77% compared to SRAM without power gating scheme. Moreover, the ability of noise immunity of SRAM with proposed approach can also be improved.

Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold currents. Minimizing leakage, by power gating logic circuits using sleep transistors gives considerable power savings. However, this technique cannot be used in sequential circuits and memory cells, as it would result in loss of stored data. In this paper, we propose a novel circuit by applying a self-bias transistor (SBT) to minimize sub-threshold leakage currents in static and dynamic circuits. This circuit with SBTs, acts as a smart switch by virtually power gating either pull-up or pull-down logic, and causes a considerable reduction in leakage currents in both active and standby modes. A benchmark is simulated with 0.18 /spl mu/m CMOS technology in the Cadence Spectre circuit simulator. Results show significant reduction in leakage power, of up to 50% on average, for all possible states simulated in static and dynamic circuits by applying this proposed self-bias transistor.

Power-gating (PG) techniques have been widely used in modern digital ICs to reduce their standby leakage power during idle periods. Meanwhile, virtual supply voltage (VVDD) of a power-gated IC is a function of strength of a PG device and total current flowing through it. Thus, the VVDD level becomes susceptible to 1) negative bias temperature instability (NBTI) degradation that weakens the PG device over time and 2) temporal temperature variation that affects active leakage current (thus total current) of the IC. To account for the NBTI degradation, the PG device must be upsized such that it guarantees a minimum VVDD level that prevents any timing failure over chip lifetime. Moreover, the PG device is also sized for the worst-case voltage drop partly resulted by a large amount of active leakage current at high temperature. However, increasing the size of the PG device to consider both effects leads to higher VVDD (thus active leakage power) than necessary at low temperature and/or in early chip lifetime. To minimize active leakage power increase due to these effects, we propose two techniques that adjust strength of a PG device based on its usage and IC's temperature at runtime. Both techniques are applied to an experimental setup modeling total current consumption of an IC in 32nm technology and their efficacy is demonstrated in the presence of within-die spatial process and temperature variations. On average of 100 die samples, they can reduce active leakage power by up to 10% in early chip lifetime.

A large amount of leakage power could be saved by increasing the number of idle virtual channels (VCs) in a network-on-chip (NoC). Low-leakage power switch is proposed to allow saving in power dissipation of the NoC. The proposed NoC switch employs power supply gating to reduce the power dissipation. Two power reduction techniques are exploited to design the proposed switch. Adaptive virtual channel technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating (PG) reduces the average leakage power consumption of proposed switch. The proposed techniques save up to 97% of the switch leakage power. In addition, the dynamic power is reduced by 40%. The traffic-based virtual channel activation (TVA) algorithm is used to determine the traffic status and send adaptation signals to PG units to activate/deactivate the VCs. The TVA algorithm optimally utilizes VCs by deactivating idle VCs to guarantee high-leakage power saving with high throughput. TVA is an efficient and flexible algorithm that defines a set of parameters to be used to achieve minimum degradation in NoC throughput with maximum reduction in leakage power. The whole network average leakage power has been reduced by up to 80% for 2-D-mesh NoC with throughput degradation within only 1%. For 2-D-torus NoC, a saving in power of up to 84% is achieved with <2% degradation in throughput. The implementation overhead of TVA is negligible.

In today's nanometric VLSI designs achieving both power and performance targets is the top most priority for design closure. Globally asynchronous locally synchronous (GALS) architectures can offer less dynamic power and improved performance due to absence of global clock. In GALS SoC architectures each synchronous blocks runs on their local clocks. Synchronous blocks communicate with each other by pausing their local clocks using an asynchronous interface which is implemented using various handshake protocols. However any synchronous block which has to wait long time for data from another block need to be in idle state and as a result will dissipate significant leakage power in nanometric designs. Power gating is an effective technique to reduce leakage power of an idle circuit in synchronous designs. However implementing such power gating interface in GALS architecture is a challenge in the absence of clock. Thus to reduce the leakage power in ideal blocks which are waiting for the data, a new GALS wrapper interface was proposed which can generate power gating sequence. To corroborate the proposed interface a GALS 8051 was implemented using Synopsys SAED 90 nm libraries. The power gating sequence of 8051 asynchronous wrappers are used to gate the power of Random Access Memory (RAM) block while Arithmetic Logic Unit (ALU) block is busy in doing arithmetic operations. The experimental results show a 30% reduction in leakage power of RAM block due to power gating.

Due to the continuous downsizing of metal oxide semi-conductor field effect transistor devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (leakage control input DEPendent) is proposed for nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various short gate (SG) fin type field effect transistor (FinFET) logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71% and 91.92% in LCINDEP SG FinFET NAND and NOR gates respectively with respect to the conventional SG FinFET NAND and NOR gates. Besides this benchmark circuits like ring oscillator and ISCAS-85 C17 show decrease in power dissipation by 24.75% and 35.5% respectively with LCINDEP technique in respect to the conventional FinFET circuits. Reliability analysis in terms of process voltage and temperature variations is performed using Monte Carlo Approach for 5000 samples, which also depicts that proposed LCINDEP technique is more reliable than the available low power techniques. The normalized standard deviations (σ/µ)% is improved by 54.68% and 43.93% for power delay product metric in the proposed technique compared to the conventional one for SG FinFET NAND and NOR gates respectively. All the simulations are performed at 16 nm technology node for FinFET logic devices using predictive technology model multigate based on BSIM-CMG on HSPICE tool.

While some leakage power reduction techniques require modification of the process technology, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter and compare three techniques: input vector control, body bias control, and power supply gating. We determine their limits and benefits in terms of the potential leakage reduction, performance penalty, and area and power overhead. The leakage power savings trends considering technology scaling are also presented. Due to the differences in the properties of datapath logic and memory structures, different implementations are recommended. Finally, the use of the "minimum idle time" parameter, as a metric for evaluating different leakage control mechanisms, is shown.

In CMOS technology, performance degradation of power is one of the foremost questions at daily vitality. In this circuit, power dissipation is increasing exponentially constantly with technology scaling down. The analog to digital converters (ADCs) are the vital branch of signal processing and communication system. In digital region power consumption and low voltage develop into wide component is difficult for conniving high speed devices and converters. In this paper we have presented a complete investigation of 3 bits flash ADC circuit by using low leakage stacked power gating technique and diode based stacked power gating technique. These techniques are reduces the leakage current and average power in standby mode effectively. In this circuit, with the stacked power gating technique, leakage current and average power is reduced is by up to 77% and 99% respectively. Diode based stacked power gating technique can be identified as the most effective technique. With this technique, leakage current is 1.241 nA at 0.7 V and average power is 3.49 nW at 0.7 V. To evaluate of power gating techniques, the simulation has been performed using cadence virtuoso tool at assorted power supply by 45nm technology.

We demonstrate that, there is an optimum reverse body bias, unique to any technology generation, that minimizes the standby leakage power consumption of an IC design implemented in that technology. We also show: (1) the optimum reverse body bias value reduces by /spl sim/2X per technology generation, and (2) the maximum achievable leakage power reduction by reverse body biasing diminishes by /spl sim/4X per generation under constant field technology scaling scenario. Optimum point occurs as a result of reduction in subthreshold leakage and an increase injunction band-to-band tunneling leakage with applied reverse bias. Therefore, new junction engineering techniques to reduce the bulk band-to-band tunneling leakage current component across the junction are needed to preserve the effectiveness of reverse body biasing for standby leakage control in future technologies.

In nanometer regime, ground bounce noise and noise immunity are becoming important metric of comparable importance to the leakage current and active power for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cell is proposed for mobile applications with low ground bounce noise. A novel approach has been introduced with stacking power gating technique for further reduction in the peak of ground bounce noise during the sleep to active mode transition. The simulation results depicts that the proposed design leads to efficient 1bit full adder cell in terms of standby leakage power, active power, ground bounce noise and propagation delay. We have performed simulations using Cadence Spectre 90nm standard CMOS technology at room temperature with supply voltage of 1V.

In integrated circuits, clocking system consumes a colossal portion of chip power, which includes switching activities of flip-flops, latches, clock distribution networks. Power gating and clock gating are two of the most effective techniques that is applied today for reducing dynamic and leakage power, respectively, in digital CMOS circuits. Power gating is essentially for reducing leakage power by switching off power supply to the nonoperational power domain of the chip during certain mode of operation. Header and footer switches, isolation cells and State Retention Flip Flops (SRFFs) used for implementing power gating. Clock gating is for reducing dynamic power by controlling switching activities on the clock path. Generally, Gate, Latch, or FF based clock gating cells used for implementing clock gating. The combined use of the two solutions, however , possess some challenges in terms of practical integration of the required control logics and power/timing overhead associated to it. Here we present an analysis in Cadence virtuoso tool using 90nm technology using a simple PIPO (parallel in parallel out) shift register. This project specifically targets the combined application of clock and power gating techniques.

In small-size Complementary Metal Oxide Semiconductor (CMOS) technology, the size of Very Large-Scale Integration (VLSI) below 90nm becomes higher and higher due to the enhancement of the short channel effect of transistors. CMOS Buffer is a very common circuit unit in VLSI. In this paper, a Pileup effect transistor (PET) is proposed to reduce the subthreshold leakage current of the CMOS buffer. The main principle of PET technology is to reduce the voltage difference between gate and source and the voltage difference between drain and source by lowering the voltage of source so as to reduce the subthreshold leakage current. Through simulation-based on Cadence and Taiwan Semiconductor Manufacturing Company (TSMC) N65 library, PET technology can reduce leakage current power consumption by about one-twelfth of the original while maintaining the function of the original CMOS buffer. PET technology has also been found to reduce current consumption in the transition state by about 40%.

When performing narrow-width computations, power gating of unused arithmetic circuit portions can significantly reduce leakage power. We deploy coarse-grain power gating in 32-bit integer arithmetic circuits that frequently will operate on narrow-width data. Our contributions include a design framework that automatically implements coarse-grain power-gated arithmetic circuits considering a narrow-width input data mode, and an analysis of the impact of circuit architecture on the efficiency of this data-width-driven power gating scheme. As an example, with a performance penalty of 6.7%, coarse-grain power gating of a 45-nm 32-bit multiplier is demonstrated to yield an 11.6x static leakage energy reduction per 8x8-bit operation.

Leakage power consumption is an increasingly serious problem in very large-scale integration circuits, especially for portable applications. Two novel approaches to leakage power minimization in static complementary metal-oxide-semiconductor circuits that employ input vector control (IVC) are investigated. The authors model leakage effects by means of pseudo-Boolean functions. These functions are linearized and incorporated into an exact (optimal) integer linear programming (ILP) model, called virtual-gate ILP, which analyzes leakage variation with respect to a circuit's input vectors. A heuristic mixed-integer linear programming (MLP) method is also proposed, which has several advantages: it is faster, its accuracy can be quickly estimated, and tradeoffs between runtime and optimality can easily be made. Furthermore, the MLP model also provides a way to estimate a lower bound on circuit leakage current. The proposed methods are used to generate an extensive set of experimental results on leakage reduction. It is shown that average leakage currents are usually 1.25 times the minimum, confirming the effectiveness of IVC. The heuristic MLP approach is shown to be approximately 13.6 times faster than the exact ILP method, whereas finding input vectors whose power consumption is only a few percent above the optimum. In addition, the lower bound estimated by the MLP model is also within a few percent of the optimal value

Modern embedded systems are often severely resource-constrained. In current research, the reduction of dynamic power has been the focus. However, with increased chip speed and density in submicron scale, the static (leakage) power consumption has become an increasingly significant fraction of the total. Indeed, a five-fold increase in leakage power per technology generation has been observed. At this pace, leakage power could soon equal dynamic power. In this paper, we investigate scheduling policies to reduce leakage power in real-time systems. We show that with simple scheduling techniques, overall leakage energy can be reduced by an order of magnitude.