Design of PLC Sequential Function Chart Based on IEC61131-3 Standard

This paper considers a whitelisting system for programmable logic controllers (PLCs). In control systems, controllers are final fortresses to continues the operation of field devices (actuators/sensors), but they are fragile with respect to malware and zero-day attacks. One of the countermeasures applicable for controllers is a whitelisting system which registers normal operations of controller behavior in a “whitelist” to detect abnormal operations via a whitelist. The previous research of the current author proposed a PLC whitelisting system with a control via a ladder diagram (LD). LD representations have a wide applicability because LDs can be implemented for all PLCs and security functions without hardware/firmware updates. However, the current status requires that all instances are manually entered in the whitelist. In this talk, we show how the setting up of the can be automatized whitelist from the PLC behavior. This paper introduces an auto-generation approach for the whitelist using sequential function chart (SFC) instead of the LD. SFC and LD are compatible representations for the PLC. Using Petri Net modeling, this paper proposes how to generate the whitelist from the SFC and how to detect abnormal operations via the whitelist. We call the SFC-based approach the model-based whitelist, the Petri Net based approach the model-based detection. Further, this paper carries out an experimental validation of the algorithms using an OpenPLC based testbed system.

Semantic Modelling of Hybrid Controllers for Robotic Cells

SFC (Sequential Function Chart) is a kind of graphic representations, which is included in IEC standards for sequential control systems. It is introduced as a specific form of PC's (Programmable Controller's) programs. For the simplicity of graphic representations and the clarity of relations of sequences, SFC is much superior to Ladder Diagram that has been so far, widely used in sequential control systems. Each element of SFC is meaningful just by the connections and SFC is strong in the representation of a flow of control sequence. However, SFC has a weak point that it is difficult to describe logic by conditions in detail like interlock relations and to represent interrupt processing. But production rules are obviously suitable for representing logic by conditions and also for interrupting process.In this paper, we propose a method to translate SFC into production rules, and to implement SFC by production rules using RTPS (Real Time Production System) in which PSL (Production System Language) is used to describe production rules. SFC has three description elements: step representing states in systems, transition representing transition conditions of systems, and link representing the connections between step and transition. We classify the flows of SFC to three types: single sequence, selective sequence and parallel sequence, and, show that each sequence can be described by pairs of transition-step. Conceming a pair of transition-step, a rule for translating the pair of transition-step into production rules is presented. These production rules will be represented by PSL. Finally, we show an example that is implemented by an RTPS.

PLC 제어 시스템은 SFC 언어를 사용하여 설계할 경우, SFC 언어를 사용하면 제어의 흐름을 이해하기 쉽고, 유지보수가 용이하며 프로그램의 기술성이 뛰어나다. SFC 언어는 단일 시퀀스, 선택 시퀀스, 병렬 시퀀스로 나누어지며, 선택 시퀀스로 프로그래밍 하면 단일 시퀀스로 프로그램할 때보다 메모리의 크기가 커져야 한다. 본 논문에서는 선택 시퀀스의 기능을 단일 시퀀스로 구현하여 메모리의 크기를 줄여서 메모리의 효율을 향상시키는 방법을 제시하고, 실례를 통해 타당성을 확인하였다.

Traffic lights are commonly used in the intersection in urban areas nowadays. In fact a network of the traffic lights regulating the urban vehicle can be viewed as a complex discrete-event system (DES). It is proved that Petri nets are one of the methodologies for modeling, analyzing and controlling on DES. A new approach via programmable logic controller (PLC) and Petri net synthesis is proposed in this paper. Firstly, we described the typical urban traffic lights control using Petri nets. Having compared with three methods for Petri nets realization, the best implementation method of the traffic lights control system was one which made with the PLC. The sequential function chart (SFC) of the PLC system is also given in the thesis. The result shown that the method has many advantages at improving flexibility and troubleshoots of system and reducing the difficulty in its realization.

Programmable Logic Controller(PLC) is the most widely utilized and plays an important role in industrial control system. The study about a PLC language is performed actively. Ladder Diagram(ID) is the most widely used in PLC. In is not suitable for describing a complex sequential logic and is very difficult to grasp the sequential flow of control logic and has the disadvantage for a maintenance. On the other hand, Sequential Function Chart(SFC) is very easy to grasp the sequential flow of control logic and has the compatability for a maintenance but has the disadvantage for describing a condition and a interlock logic. In this paper, we propose the method that describe the interlock logic using management step, and confirm his feasibility through a actual examples.

Proposed new troubleshooting methods for programmable controllers (PCs). Through studies of field applications in the tire industry the sequential function chart (SFC) is recognized as not only a powerful substitution for ladder logic diagram but also as useful in machine trouble diagnosis. Typical enhancements of SFC as self diagnostic function are; 1) to search the conditions which cause the machine to halt, 2) to collect logging table data for the historical program paths analysis, and 3) to specify the cause of the trouble by tracing back 1) and 2). This paper discusses the self diagnostic functions by SFC and its implementation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Grafcet or function charts for control systems is an international standard used for the specification and the implementation of logic controllers in manufacturing systems [1], [2]. This model is the basis of the Sequential Function Charts (SFC) international standard used for the implementation of logic controllers. Throughout the twenty years that have passed since it was defined [3], Grafcet is becoming widely used in the industry [4] and in education [5]. The main contribution of Grafcet, which uses a Petri-net like formalism, is that it allows a clear modelling of inputs and outputs and of their relations. It also allows modelling of concurrency and synchronisation. This makes Programmable Logic Controllers (PLCs) more tractable and simplifies the simulation of the control logic of the system. Many PLC builders today use the Grafcet as a specification and/or as a programming language. Among the large companies using it widely or recognising it as an internal standard are: Siemens, Renault, Peugeot, Michelin, and others. However, and in spite of its advantages, Grafcet has long been criticised because it is not supported by a formal foundation that allows to insure correctness and safety requirements on the one hand, and because it lacks adequate methodology that allows an efficient development of high quality models in the case of complex systems on the other.KeywordsDiscrete EventProof SystemDiscrete Event SystemProgrammable Logic ControllerLiveness PropertyThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Programmable logic controllers are commonly used in automation systems. Continuously growing demands result in the growth of control program complexity. The classic approach, based on programmatic serial-cyclic execution, results in an unacceptable extension of response time. To overcome long response time massive parallel program execution is proposed. It utilize direct in hardware program implementation in field programmable devices. The paper brings a formal method of representing control programs using flow graphs and enabling single cycle computations. The developed method accepts ladder diagrams (LD) and sequential function charts (SFC), according to IEC61131-3 standard requirements. It is capable of handling logic and arithmetic computations, enabling its hardware mapping. The intermediate form is optimized using flow graph representation and BDDs for analyzing logic dependencies. The BDD representation of logic dependencies enables direct mapping to lookup tables of a selected FPGA family. All the above steps deliver high-performance and direct hardware implementation of the control program given by standard languages. The controller response time is short, predictable, and independent from logic conditions during program execution.

Fault Detection and Isolation on Hybrid Systems by SFC

Validation of a SFC Software Specification by Using Hybrid Automata

Design Method on Optimal Flexible Manufacturing Systems

To facilitate efficient procedure synthesis, the extended finite automata are adopted in this work to model all components in a chemical process. The intended operation is divided into several stages and each characterized with a set of unique features, e.g., stable operation, condition adjustment, material charging and/or unloading, etc. The control specifications of every stage should then be stipulated accordingly and also described with automata. The observable event traces (OETs) embedded in this system can be produced by synchronizing all aforementioned automata. The candidate operating procedures are summarized with sequential function charts (SFCs) on the basis of these OETs. The commercial package ASPEN Plus Dynamic has been used to validate these SFCs in simulation studies.

Test sequence construction from SFC specification

The logic control program is usually specified by drawing the Petri net in terms of interface with the electro-mechanical devices and the environment of the system. In such case it is not immediately evident that the control system behaves in a satisfactory way. Industrial engineers prefer frequently a form of specification, like interpreted Petri Net, sequential function chart (SFC), Grafcet or Grafchart. On the other hand, some popular techniques are informal and do not provide means to validate the design. In the paper, modelling, analysis and synthesis of logic controller described by Petri nets is presented. Additional, the use of design/CPN system for modelling, testing and analysis of logic controllers described by means of coloured, interpreted Petri nets is shown. The proposed methods are especially useful in designing of industrial application specific logic controller (ASLC) with FPGA.