Design of Reed-Solomon Encoder for Error Detection in DRAM Cells

Reed-Solomon (RS) codes are error-correcting codes used in many of today's communication systems. RS encoding and decoding are typically implemented using dedicated hardware elements used in ADSL modems and digital TV. In this paper we propose using software in lieu of a hardware-based RS de-coder. This is accomplished using the Berlekamp-Massey algorithm, implemented on a programmable DSP. This software-based RS decoder using Berlekamp-Massey is implemented on Motorola's MSC8101 StarCore DSP. In order to evaluate the algorithm we use the following criteria: computation cost; cycle count, critical paths in the decoding scheme, and error location in the codeword. Furthermore, we examine the effect of changing the RS code's k, t parameters and its primitive polynomial in real-time implementation. The Berlekamp-Massey algorithm operates over finite field arithmetic, whose steps, as applied on the StarCore DSP, are discussed in detail and specifically evaluated using the assembly code for the syndrome search. We conclude that the Berlekamp-Massey algorithm, used for RS decoding, should be implemented using long codewords.

An efficient encoder circuit for a systematic Reed-Solomon code with arbitrary parity positions is presented. In contrast to the Reed-Solomon encoder circuits widely available today, the parity symbols produced by this encoder are not restricted to form a block of consecutive parity symbols at the beginning or end of the codeword, but may be spread arbitrarily within the codeword. A general structure of the parity-check matrix for such a code is derived by exploiting the special structure of Vandermonde matrices. From this general parity-check matrix, an expression for the calculation of the Reed-Solomon parity symbols at arbitrary positions within the codeword is found and an efficient hardware implementation of the proposed encoder is designed.

The performance of a communication system having almost the same spectral efficiency as a trellis coded modulation (TCM) system with r = 2/3 convolutional encoding and 8-ary phase-shift keying (8-PSK) modulation is investigated. TCM is a common solution to the problem of adding forward error correction (FEC) coding without an attendant increase in channel bandwidth. The primary drawback to TCM is that the achievable coding gain is limited by the maximum practical number of states in the convolutional encoder. The alternative system considered uses (63, 37) Reed-Solomon (RS) encoding. The six-bit symbols at the output of the Reed-Solomon encoder undergo serial-to-parallel conversion to two three-bit symbols, which are then independently transmitted on the in-phase and quadrature components of the carrier using 8-ary biorthogonal keying. This system has a null-to-null bandwidth of 0.993R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sub> , which is 0.7% smaller than TCM with r = 2/3 convolutional encoding and 8-PSK modulation. The two waveforms are compared for the relatively benign case where additive white Gaussian noise is the only noise present as well as when pulse-noise interference is present.

This paper proposes a generator polynomial model-based eye diagram estimation method for the error-correction codes (ECCs), which are the Bose–Chaudhuri–Hocquenghem (BCH) code and the Reed–Solomon (RS) code. The ECCs compensate for the channel loss at the bit level, so most of the systems include the ECC block. The BCH and RS codes are the generator polynomial-based ECCs; this paper proposes the generator polynomial model-based method. The model provides the accurate probability density function of the code words for the BCH and RS code. Thus, the proposed method is capable of achieving the signal integrity analysis for the system level. For verification, we design the BCH and RS encoders. The estimated eye diagrams are nearly the same as that of the transient simulation for the BCH and RS codes. Furthermore, the voltage bathtub curves are the same up to 10−8. For a smaller bit-error rate value, the proposed method only provides the bathtub curve. This paper successfully verifies the eye diagram estimation method for the BCH and RS codes.

The Reed-Solomon (RS) (255,223) code is a powerful burst error correcting code, and it can correct any combination of 16 or fewer RS symbols in error per codeword. Based on the Berlekamp's bit-serial multiplication algorithm, we design and implement a sounding rocket-borne RS (255, 223) encoder with 2-depth symbol interleaving capability. The implementation result of the encoder on single-chip Xilinx FPGA XC3S400 is presented. The encoder is tested by three classes of RS symbols, and the test results indicate that the designed RS (255, 223) encoder is highly efficient and suitable for applying on sounding rocket missions.

This paper presents a parallel architecture for a high-speed Reed-Solomon (RS) encoder and decoder (codec) LSI. Since the architecture allows H symbols to be processed in parallel the codec LSI achieves a data rate of mLH b/s. where m is the symbol size (m bits per symbol), L is the clock frequency of the circuit, and H is an arbitrary integer. As an example, we investigate hardware complexity, delay and critical path length for a (255.251) RS code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with, this parallel architecture is that the encoder's critical path length increases with H, the proposed architectures is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that parallel RS codecs, which can keep up with optical transmission rates, i.e. several giga bits/sec. could be implemented on one LSI chip, using current CMOS technology.

21st century is an era of wireless world. The cause of the current trend for wireless applications is the improved data rate for multifarious applications of communication. But during communication, the data might be distorted due to impairments of channels. Reduction of error due to noisy channels becomes critical. Novel high speed VLSI architecture for encoding Reed Solomon codes are presented in this paper. Pipelining and parallelizing allows inputs to be transmitted at high rates within minimum delay. The speed bottleneck in the basic LFSR based Reed Solomon encoder is eliminated by proposing a new modification of the LFSR into the form of an Infinite Impulse Response (IIR) filter. The proposed architecture results in critical path with less hardware overhead. An example illustrating the parallel and pipelined architecture of an encoder is given for (15, 9) RS code. The proposed architecture produces a delay of 2.33nS and its speed is of 428.27MHz.

Adaptive Reed–Solomon coding and envelope detection of photonic vector signal in V-band radio over fiber system

This paper presents a high-throughput variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS (255,239) code but also various shortened RS codes. Moreover, the variable-length architecture provides low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-nm CMOS standard cell technology, the proposed variable-length RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-Gbps data rate at clock frequency 300 MHz.

This paper presents a high-speed low-complexity Reed-Solomon (RS) decoder architecture using a novel pipelined recursive modified Euclidean (PrME) algorithm block for very high-speed optical communications. The RS decoder features a low-complexity key equation solver using a PrME algorithm block. The recursive structure enables the novel low-complexity PrME algorithm block to be implemented. Pipelining and parallelizing allow the inputs to be received at very high fiber-optic rates, and outputs to be delivered at correspondingly high rates with minimum delay. This paper presents the key ideas applied to the design of an 80-Gb/s RS decoder architecture, especially that for achieving high throughput and reducing complexity. The 80-Gb/s 16-channel RS decoder has been designed and implemented using 0.13-/spl mu/m CMOS technology in a supply voltage of 1.2 V. The proposed RS decoder has a core gate count of 393 K and operates at a clock rate of 625 MHz.

This paper presents a novel approach to implementing multiplication of Galois Fields with . Elements of GF() can be represented as polynomials of degree less than N over GF(2). Operations are performed modulo an irreducible polynomial of degree n over GF(2). Our approach splits a Galois Field multiply into two operations, polynomial-multiply and polynomial-remainder over GF(2). We show how these two operations can be implemented using the same hardware. Further, we show that in many cases several polynomial-multiply operations can be combined before needing to a polynomial-remainder. The Sandblaster 2.0 is a SIMD architecture. It has SIMD variants of the poly-multiply and poly-remainder instructions. We use a Reed-Solomon encoder and decoder to demonstrate the performance of our approach. Our new approach achieves speedup of 11.5x compared to the standard SIMD processor of 8x.

Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurring in the transmission process. Since the decoding process for RS codes is rather computation-extensive, special-purpose hardware structures are often necessary for it to meet the real-time requirements. In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for RS decoding. The architecture is developed based on a time domain algorithm using the remainder decoding concept. A prominent feature of the proposed system is that, for a t-error-correcting RS code with block length n, it involves only 2t consecutive symbols to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the same algorithm without using the remainder decoding concept. The proposed RS decoder can process one data block every n clock cycles, i.e., the average decoding rate is one symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains significant improvements in hardware complexity and latency.

In this paper, a low-power Reed-Solomon (RS) decoder for STM-16 optical communications is presented. It mainly contains one (255,239) RS decoder and four 2 K-bit embedded memory for correcting the received codewords. Except the novel syndrome calculator reducing half the syndrome computations, our proposal also features a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The (255,239) RS decoder is implemented by 0.25 /spl mu/m CMOS 1P5M standard cells with gate counts of 32.9 K and area of 2.03 mm/sup 2/. Simulation results show our approach can work successfully at the data rate of 2.5-Gbps and achieve 80% reduction of power dissipation on the average.

In this paper, we proposed a multiple description distributed image coding system for mobile wireless transmission. The innovations of proposed system are two folds: First, when MDC is applied to wavelet subband based image coding; it is possible to introduce correlation between the descriptions in each subband. At the encoder, the correlation information is encoded by systematic Reed Solomon (RS) encoder. Only the parity check bits are sent to channel. At the receiver, when part of descriptions are lost, however, their correlation information are available, the Wyner Ziv decoder can still recover the description by using the correlation information and the partly received description as noisy version and the side information. Secondly, in each description, we use multiple bitstream image coding to achieve error robust transmission. In conventional entropy subband coding, the first bit error may cause the decoder to discard all subsequent bits. A multiple bitstream image encoding is developed based on the decomposition of images in the wavelet domain. We show that such decomposition is able to reduce error propagation in transmission, thus to achieve scalability on PSNR performance over the changes of BER, Experimental result shows that the PSNR could be improved with the same coding rate.

This paper presents a high-speed low-complexity three-parallel Reed-Solomon (RS) decoder for 6-Gbps mmWave WPAN systems. Three-parallel processing is used to achieve 6-Gbps data throughput and low hardware complexity. Three-way parallelizing for syndrome computation and error correction allow the inputs to be received at very high data rates and the outputs to be delivered at correspondingly high rates with a minimum delay. The proposed three-parallel RS decoder has been implemented 90 nm CMOS technology optimized for a 1.2 V supply voltage. The implementation result shows that the proposed RS decoder can operates at a clock frequency of 400 MHz and has a data throughput 9.6-Gbps. The proposed three-parallel RS decoder architecture has a much higher data processing rate and low hardware complexity, and also can be adapted in the FEC devices for mmWave WPAN systems with a data rate of 6 Gbps and beyond.