Design Procedure Based on VHDL Language Transformations

Background: In recent years, the rising demand for high-performance radar systems in aeronautics, astronautics, national defense, and civil communication has driven the widespread application of phased-array technology. The design of beam controllers, the core of phased-array systems, faces many challenges. Traditional implementation schemes are usually based on application-specific integrated circuits (ASIC) or discrete components, which have a long development cycle, poor flexibility, and limited adaptability. Field-programmable gate arrays (FPGA), with their high parallelism, reconfigurability, and powerful signal processing capabilities, offer a new way to implement phased-array control systems. But FPGA design has traditionally relied on register transfer level (RTL) description, which is inefficient and struggles to keep up with the rapid iteration of complex algorithms. With the development of high-level synthesis (HLS) technology, it has become possible to develop FPGAs using high-level languages such as C/C++. However, improving development efficiency while ensuring hardware performance remains a key issue in the design of phased-array beam controllers. Materials and Methods: This study employs an HLS - RTL co - design method to build a phased - array beam controller. This approach combines the strengths of HLS's efficient algorithm implementation and RTL's precise hardware interface control. The system architecture consists of three parts: the host - machine control layer, FPGA processing layer, and phase - control output layer. In the FPGA processing layer, the core beam - forming algorithm is implemented via HLS. Based on phased - array principles, this algorithm converts target angles to wave vectors and calculates phase - compensation values for each element in an 8×8 array. Pipelining and parallel processing techniques are used in the HLS design to optimize algorithm throughput and latency. The phase - control output layer, designed with RTL, repackages 64 calculated phase values and distributes them to 16 physical phase - shifter chips. Each phase - shifter manages four elements and receives control data through an SPI interface. Results: The proposed FPGA-based phased-array beam controller design in this paper has successfully achieved high - speed, high - precision beam control. By using the HLS - RTL co - design method, it has solved the problem of low algorithm implementation efficiency in traditional FPGA development and ensured the high performance and reliability of hardware interfaces. Experimental results indicate that the system meets or surpasses design targets on key performance indicators. Its end - to - end latency is kept within 130μs, it supports an angle update rate of over 5,000 times per second, and can satisfy the requirements for tracking highly dynamic targets in practical applications. Conclusion: The major contributions of this research are as follows: presenting an HLS - RTL co - design methodology for complex FPGA system development; designing an efficient phased - array beam - forming algorithm and its hardware implementation; and developing a flexible and scalable phased - array control system architecture that supports different array configurations. These findings are highly significant for beamforming technologies in phased - array radar and 5G communication systems, as well as for other FPGA applications requiring high - speed signal processing.

The growing complexity of modern digital design makes designers shift toward starting design exploration using high-level languages, and generating register transfer level (RTL) design from system level modeling (SLM) using high-level synthesis or manual transformation. Unfortunately, this translation process is very complex and may introduce bugs into the generated design. In this paper, we propose a novel SLM and RTL sequential equivalence checking method. The proposed method bases on Finite state machines with datapath (FSMD) equivalence checking method. The proposed method recognizes the corresponding path-pairs of FSMDs using machine learning (ML) technique from all the paths. And then it compares the corresponding path-pairs by symbolic simulation. The advantage of our method is that it separates the corresponding path-pairs from all the paths and avoids blind comparisons of path-pairs. Our method can deal with greatly different SLM and RTL designs and dramatically reduce the complexity of the path-based FSMD equivalence checking problem. The promising experimental results show the efficiency and effectiveness of the proposed method.

The rapidly increasing complexities of hardware designs are forcing design methodologies and tools to move to the Electronic System Level (ESL), a higher abstraction level with better productivity than the state-of-the-art Register Transfer Level (RTL). Behavioral synthesis, which automatically synthesizes ESL behavioral specifications to RTL implementations, plays a central role in this transition. However, since behavioral synthesis is a complex and error-prone translation process, the lack of designers' confidence in its correctness becomes a major barrier to its wide adoption. Therefore, techniques for establishing equivalence between an ESL specification and its synthesized RTL implementation are critical to bring behavioral synthesis into practice. The major research challenge to equivalence checking for behavioral synthesis is the significant semantic gap between ESL and RTL. The semantics of ESL involve untimed, sequential execution; however, the semantics of RTL involve timed, concurrent execution. We propose a sequential equivalence checking (SEC) framework for certifying a behavioral synthesis flow, which exploits information on successive intermediate design representations produced by the synthesis flow to bridge the semantic gap. In particular, the intermediate design representation after scheduling and pipelining transformations permits effective correspondence of internal operations between this design representation and the synthesized RTL implementation, enabling scalable, compositional equivalence checking. Certifications of loop and function pipelining transformations are possible by a combination of theorem proving and SEC through exploiting pipeline generation information from the synthesis flow (e.g., the iteration interval of a generated pipeline). The complexity brought by bubbles in function pipelines is creatively reduced by symbolically encoding all possible bubble insertions in one pipelined design representation. The result of this dissertation is a robust, practical, and scalable framework for certifying RTL designs synthesized from ESL specifications. We have validated the robustness, practicality, and scalability of our approach on industrial-scale ESL designs that result in tens of thousands of lines of RTL implementations.

Neural networks (NNs) are used in numerous applications such as audio–video processing and image classification. NNs can address the limitations of the traditional computer algorithms. Recently, the research utilizing field-programmable gate arrays (FPGAs) to implement NNs is on the rise due to low power dissipation, easy and fast reconfigurability offered by these platforms. This is due to the research and development efforts put into the design optimization to improve the throughput of FPGAs. The integration of appropriate hardware with advanced artificial intelligence (AI) software presents many challenges. This paper offers a generalized model of NNs on a FPGA device. In addition, it presents the design process for the high-level synthesis (HLS) tools to implement the project on FPGA. This paper shows the results of latency, timing, pre- and post-synthesis, implementation, and hardware utilization on Xilinx FPGA target device. In this paper, NN for XOR logic gate operation is performed and verified by using HLS tool, and FPGA implementation is proposed. The NN and backpropagation algorithm are developed in high-level programming languages like Python, Java, C, C++. The training part of the NN has been done by using open-source software Dev C++, and tuned weights are taken to Xilinx Vitis HLS. Simulation, synthesis, and implementation are performed by using Xilinx Vitis HLS and Vivado 2020.1 electronic design automation (EDA) tools. NN architecture with tuned weights is implemented on Xilinx ZYNQ FPGA target device. This paper shows that we were able to achieve latency in one clock cycle interval through pipeline and array partition.KeywordsHigh-level synthesis (HLS)Neural networks (NNs)Register transfer level (RTL)Field-programmable gate arrays (FPGAs)Systems on chip (SOC)Artificial intelligence (AI)Graphic processing units (GPUs)Generalized NNs (GNN)Recurrent neural network (RNN)Feed-forward neural networks (FFNNs)

High-Level Synthesis (HLS)-based VLSI design flows allow designers to start from high-level specifications in a general-purpose programming language like C/C++ and automatically generate an optimized hardware design in a hardware description language (HDL) like Verilog or VHDL. Supply of compromised computer-aided design (CAD) tools by an electronic design automation (EDA) vendor to the chip designers is a great threat that adversely affects the horizontal semiconductor business model. Recent works have examined the potential for security issues induced by a compromised HLS CAD tool and demonstrated how HLS is a prime candidate for hardware Trojan (HT) insertion into any underlying design since it is hard to correlate the high-level description to the generated register-transfer level (RTL) code. Further, it has been shown that the use of compiler-generated intermediate representation (IR) as a likely attack vector for inserting HT in the RTL during an HLS-based IC design flow, taking advantage of the lack of automated methods to analyse logic inside a complex LLVM IR. In this work, we propose, implement, and evaluate a novel HLS security verification framework by leveraging the modern large language models (LLMs). Specifically, we focus on detecting the HTs introduced using Black-Hat HLS and HLS-IRT toolchain by performing functional verification using LLM. The experimental results show that LLMs have an impressive ability to analyse and automatically identify these hardware security anomalies.

A short time-to-market is very important for a chip, and verification takes the most (about 70%) of its design time. Network interface controller (NIC) is a key component for a supercomputer and other computing systems. To reduce verification time for such a market-demanding product plays a great role in relevant system design. In this paper, a functional verification accelerator NICFlex is presented for a register transfer level (RTL) NIC design. NICFlex accelerates verification process by both a software part and a hardware part. The software part runs as a simulation thread, and the hardware part is mapped into field programmable gate array (FPGA) logic together with a NIC wrapper. Compared to a conventional simulation verification method using ModelSim, NICFlex can accelerate the functional verification of an RTL NIC design for hundreds of times or more. With extension, NICFlex is promising for any functional verification acceleration of a generic RTL design.

High-level synthesis (HLS), which automatically synthesizes a register-transfer level (RTL) circuit from a behavioral description written in a high-level programming language such as C/C++, is becoming a more popular technique for improving design productivity. In general, HLS tools often generate a circuit with a larger area than those of hand-designed ones. One reason for this issue is that HLS tools often generate multiple instances of the same module from a function. To eliminate such a redundancy in circuit area in HLS, HLS tools are capable of sharing modules. Function-level module sharing at a behavioral description written in a high-level programming language may promote function reuse to increase effectiveness and reduce circuit area. In this paper, we present two HLS techniques for module sharing at the function level.

In this paper, an integer linear programming (ILP) based algorithm is presented that considers resource constraints and optimize leakage delay product (LDP) using a precharacterized register transfer level (RTL) library. For nanoscale CMOS (nano-CMOS) circuits leakage is a predominate form of power dissipation. Leakage optimization at the early stage of design cycle, such as during high-level synthesis is quite few. Two techniques, dual-T ox (DOXCMOS) and dual-V th (DTCMOS) technology are explored during the high-level synthesis for leakage optimization. The leakage is assumed to be sum of gate-oxide leakage and subthreshold leakage. Register transfer level (RTL) components are characterized for DOXCMOS and DTCMOS technology accounting for process variations, which is an important issue for nanoscale circuits. Experiments were performed on several high-level synthesis benchmark circuits, which show an average reduction of 79% gate leakage and 76% of subthreshold leakage for DOXCMOS and DTCMOS technology, respectively. It is observed that DOXCMOS technology based optimization out performed the results from DTCMOS technology based optimization.

Automated hardware synthesis starting from the register transfer level (RT-level) VHDL description is well established. However, starting the design on a higher abstraction level than the RT-level is one of the major problems within the VHDL based system synthesis. We present a novel design procedure called SYLANT (Synthesis based on Language Transformations), which uses the methodology of high-level synthesis. It starts from the abstract functional model and produces an RT-level description through successive language transformations. The biggest advantage of this method is that no other description technique than the standard VHDL is considered. The intermediate VHDL code is accessible to the designer, the circuit model can be simulated after each design step. Different algorithms can be implemented for any step, depending on the applied technology dependent information and various RT-level architectures can be obtained. The output VHDL format is suitable to continue the design flow with RT-level based synthesis tools.

Today, the most common abstraction level for manual design capture is at the so called register transfer level. At this level, all synchronous registers, latches and the combinational logic between the sequential elements are described in a hardware description language such as Verilog or VHDL. The description is then transformed into logic gate implementations based on a technology specific cell library, a procedure known as logic synthesis. This allows a designer to handle more complex design because detailed manual analysis need not be made at the logic gate level that is more tedious and error prone. Register transfer level is certainly not the only starting point for automated hardware synthesis. The analysis and synthesis of digital circuits are still being pushed toward even higher level of abstraction for manual manipulation. For example, macro block level specification and synthesis has been practiced in some design areas. The register transfer and macro block level design methodologies are part of the architecture and system level techniques to be discussed in this chapter.

Hardware co-processors are used for accelerating specific compute-intensive tasks dedicated to video/audio codec, encryption/decryption, etc. Since many of these data-processing tasks already have efficient software algorithms, one could reuse those to synthesize the co-processor IPs. However, such software algorithms are usually sequential and written in C/C++. High-level Synthesis (HLS) helps in converting software implementation to register transfer level (RTL) hardware design. Such co-processor based systems show enhanced performance but often have greater power/energy consumption. Therefore, the automated synthesis of such accelerator IPs must be power-aware. Downstream power savings features such as clock-gating are unknown during HLS. Designer is forced to take such power-aware decisions only after logic synthesis stage, causing an increase in design time and effort. In this paper, we present a design automation solution to facilitate various granularities of clock-gating at high-level C description of the design.

Due to the rapidly increasing complexity in hardware designs and competitive time to market trends in the industry, there is an inherent need to move designs to a higher level of abstraction. Behavioral Synthesis is the process of automatically compiling such Electronic System Level (ESL) designs written in high-level languages such as C, C++ or SystemC into Register-Transfer Level (RTL) implementation in hardware description languages such as Verilog or VHDL. However, the adoption of this flow is dependent on designers' faith in the correctness of behavioral synthesis tools. Loop pipelining is a critical transformation employed in behavioral synthesis process, and ubiquitous in commercial and academic behavioral synthesis tools. It improves the throughput and reduces the latency of the synthesized hardware. It is complex and error-prone, and a small bug can result in faulty hardware with expensive ramifications. Therefore, it is critical to certify the loop pipelining transformation so that designers can trust the behaviorally synthesized pipelined designs. Certifying a loop pipelining transformation is however, a major research challenge because there is a huge semantic gap between the input sequential design and the output pipelined implementation, making it infeasible to verify their equivalence with automated sequential equivalence checking (SEC) techniques. Complex loop pipelining transformations can be certified by a combination of theorem proving and SEC: (1) creating a certified pipelining algorithm which generates a reference pipeline model by exploiting pipeline generation information from the synthesis flow (e.g. the iteration interval of a generated pipeline) and (2) conduct SEC between the synthesized pipeline and this reference model. However, a key and arguably, the most complex component of this approach is the development of a formal, mechanically verifiable loop pipelining algorithm. We show how to systematically construct such an algorithm, and carry out its verification using the ACL2 theorem prover. We propose a framework of certified pipelining primitives which are essential for designing pipelining algorithms. Using our framework, we build a certified loop pipelining algorithm. We also propose a key invariant in certifying this algorithm, which links sequential loops with their pipelined counterparts. This is unlike other invariants that have been used in proofs of microprocessor pipelines so far. This dissertation provides a framework for creating certified pipelining algorithms utilizing a mechanical theorem prover. Using this framework, we have developed a certified loop pipelining algorithm. This certified algorithm is essential in the overall approach to certify behaviorally synthesized pipelined designs. We demonstrate the

Using RTL (Register Transfer Level) models for the verification of complex hardware designs involves reducing the state space of designs using various abstraction techniques. In this paper, we propose faster and earlier verification of hardware designs at a level of abstraction above RTL. We consider a high-level (above RTL) hardware model that uses atomic rules to describe the behavior of a design, which can then be synthesized to RTL code. Bluespec System Verilog (BSV) is an example of such a high-level specification language. We propose a methodology for verification of BSV models using Spin, which is a Model Checking tool. Verification of high-level BSV models may avoid the need for using abstraction techniques since such models already ignore various low-level details that are irrelevant for verifying a design's behavioral properties. Moreover, using our proposed methodology different behaviors of BSV models can be efficiently verified at high-level aiding in faster verification.

Developing FPGA implementations with an input specification in a high-level programming language such as C/C++ or OpenCL allows for a substantially shortened design cycle compared to a design entry at register transfer level. This work targets high-level synthesis (HLS) implementations that process large amounts of data and therefore require access to an off-chip memory. We leverage the customizability of the FPGA on-chip memory to automatically construct a multi-cache architecture in order to enhance the performance of the interface between parallel functional units of the HLS core and an external memory. Our focus is on automatic cache sizing. Firstly, our technique determines and uses up unused left-over block RAM resources for the construction of on-chip caches. Secondly, we devise a high-level cache performance estimation based on the memory access trace of the program. We use this memory trace to find a heterogeneous configuration of cache sizes, tailored to the application's memory access characteristic, that maximizes the performance of the multi-cache system subject to an on-chip memory resource constraint. We evaluate our technique with three benchmark implementations on an FPGA board and obtain a reduction in execution latency of up to 2× (1.5× on average) when compared to a one-size-fits-all cache sizing. We also quantify the impact of our automatically generated cache system on the overall energy consumption of the implementation.

High-level synthesis operates on internal models known as control/data flow graphs (CDFG) and produces a register-transfer-level (RTL) model of the hardware implementation for a given schedule. For high-level synthesis to be efficient it has to estimate the effect that a given algorithmic decision (e.g., scheduling, allocation) will have on the final hardware implementation (after logic synthesis). Currently, this effect cannot be measured accurately because the CDFGs are very distinct from the RTL/gate-level models used by logic synthesis, precluding interaction between high-level and logic synthesis. This paper presents a solution to this problem consisting of a novel internal model for synthesis which spans the domains of high-level and logic synthesis. This model is an RTL/gate-level network capable of representing all possible schedules that a given behavior may assume. This representation allows high-level synthesis algorithms to be formulated as logic transformations and effectively interleaved with logic synthesis.