Designing a Doherty Power Amplifier Without Offset Compensation Lines

This article presents the methodology for designing triple-mode Doherty power amplifier (DPA) with multi-band operation and extended high efficiency range. It is illustrated that three different Doherty operation modes can be realized by simply re-setting the gate bias voltages while the DPA circuits keep unchanged. By employing a novel reciprocal gate bias DPA architecture, five operation bands have been achieved by the proposed DPA with larger than 9 dB high efficiency power range. The active load modulation process and theoretical performance of proposed DPA are analyzed in detail for each mode. For verification, a commercial GaN transistors-based DPA is designed and implemented with 1.76–1.96 GHz band in Mode I, 1.13–1.20/2.48–2.58 GHz bands in Mode II and 0.7–0.76/2.34–2.40 GHz bands in Mode III. The fabricated DPA achieves 7.0–10.5 dB saturation gain, 44.18–46.86 dBm peak output power and 41.9%–61.5% back-off efficiency. When stimulated by a 10 MHz long term evolution (LTE) modulation signal with 8.6 dB peaking-to-average ratio (PAPR), the adjacent channel power ratio (ACPR) of the fabricated DPA is better than −45 dBc after digital pre-distortion at 0.73, 1.18 and 1.85 GHz.

ABSTRACTIn this article, we present a simplified Doherty power amplifier (DPA) architecture for the easy implementation of dual‐band operation. The proposed DPA structure eliminates the 35 Ω quarter wavelength impedance inverters used in the conventional DPAs by matching the output impedances of the carrier and peak amplifiers of the DPA to other values (e.g., 100 Ω). The electrical lengths of the offset line and the phase compensation line are carefully chosen to enhance the Doherty effect (high efficiency at back‐off power level) at two assigned frequency bands. Broadband matching networks are also designed to increase the operation bandwidths at the two designed bands. To prove the design concept, a dual‐band DPA is designed and measured. In the first frequency band (550–650 MHz), the designed DPA provides 60.6–76.3% drain efficiency (DE) at full output power, 46–54.9% DE at 6 dB of output power back‐off (OBO); in the second frequency band (950–1050 MHz), the designed DPA provides 51.4–61.2% DE at full output power, 35–38% DE at 6 dB of OBO. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:953–956, 2015

A comparison between a fully integrated Doherty power amplifier (DPA) and outphasing power amplifier (OPA) for fifth Generation (5G) wireless communications is presented in this paper. Both amplifiers are integrated using pHEMT transistors from the OMMIC’s 100 nm GaN-on-Si technology (D01GH). After a theoretical analysis, the design and layout of both circuits are presented. The DPA uses an asymmetric configuration where the main amplifier is biased in class AB and the auxiliary amplifier is biased in class C, while the OPA uses two amplifiers biased in class B. In the comparative analysis, it has been observed that the OPA presents a better performance in terms of maximum power added efficiency (PAE), while the DPA provides higher linearity and efficiency at 7.5 dB output back-off (OBO). At a 1 dB compression point, the OPA exhibits an output power of 33 dBm with a maximum PAE of 58.3% compared to 44.2% for the DPA for an output power of 35 dBm, and at 7.5 dB OBO, the DPA achieves a PAE of 38.5%, while the OPA achieves 26.1%. The area has been optimized using absorbing adjacent component techniques, resulting in an area of 3.26 mm2 for the DPA and 3.18 mm2 for the OPA.

This paper presents a linear Doherty power amplifier (DPA) in microstrip technology designed at 1.7 GHz, for long-term evolution (LTE) applications. The DPA has been implemented using a low-cost GaAs HEMT with adoption of different drain bias voltage for main and auxiliary amplifiers to increase the overall gain. Measured performance of the proposed DPA across 1.48–1.83 GHz shows an output power of 31.5 dBm with 60% power added efficiency (PAE) at the 1-dB compression point (P1dB). The PAE is maintained higher than 50%, over 6 dB of output back-off range, and higher than 30% over 10 dB output power back-off. Moreover, the linearity performance of the designed DPA in terms of IMD3 is tested by applying a two-tone signal to the input of DPA which shows the IMD3 of less than −27 dBc at an output power of 31.5 dBm and −33 dBc at about 6 dB back-off power.

An average power tracking (APT) Doherty power amplifier (PA) is analyzed in terms of its biasing voltage condition, efficiency, and output power. And the drain and gate bias voltages are optimized for operation at different output power conditions. The Doherty power amplifier is designed using 45 W gallium nitride (GaN) high electron mobility transistors (HEMT) for the carrier and peaking cells at 1.94 GHz. The bias voltages are controlled for each average power level(42.9 dBm, 39.9 dBm, 37 dBm). The measured drain efficiencies and gains are 53.2%, 12.8 dB at 42.9 dBm and 54.3%, 11.2 dB at 39.9 dBm and 53.4%, 9.1 dB at 37 dBm for a 10 MHz LTE signal with a 6.5 dB PAPR. This result demonstrates that the Doherty PA can be reconfigured for different average output powers using the bias voltage control method.

This letter presents a bias-adjusted group digital predistortion (DPD) method to enhance linearization in multiple-input multiple-output (MIMO) transmitters with hybrid beamforming. By introducing a cross-normalized mean square error (CNMSE) metric, the nonlinearity consistency of multiple Doherty power amplifiers (DPAs) sharing radio frequency (RF) chains is quantitatively evaluated. A reference state is established using the worst-performing DPA, and the gate biases of other DPA are optimized to minimize CNMSE, aligning their nonlinear characteristics. This simplifies DPD training to a single-channel paradigm. Experiments with four DPAs under a 64-quadrature amplitude modulation (QAM) signal (200 MHz bandwidth) demonstrate a 6.77 dB adjacent channel power ratio (ACPR) improvement over the baseline and 4.51 dB gain versus conventional DPD, validating efficient multi-DPA linearization for resource-constrained MIMO systems.

A quarter-wavelength impedance transformer as well as a number of other factors limit the bandwidth (BW) of Doherty power amplifiers (PAs). We utilize the lower Q of a quarter-wave length transformer and propose a phase compensation circuit and an additional offset line to be incorporated into the matching net works for an enhanced BW of the Doherty PA. The quarter-wave length transformer and the final output circuit have the same Q. Input dividing networks are also analyzed for operation of broad BW. The Doherty PA for long term evolution (LTE) applications is integrated into a 1.4 × 1.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die using an InGaP/GaAs hetero junction bipolar transistor (HBT) process. For an LTE signal with a 7.5-dB peak-to-average power ratio (PAPR) and a 10-MHz BW, the PA with a supply voltage of 4.5 V delivers a power-added ef ficiency (PAE) of 36.3% and an adjacent channel leakage ratio (ACLR) of -32 dBc with an average output power of 27.5 dBm at a frequency of 1.85 GHz. Across frequencies from 1.6-2.1 GHz, the PA performs with a PAE of more than 30%, a gain of more than 28 dB and an ACLR of less than -31 dBc at an average output power of 27.5 dBm while satisfying the standard spectrum mask. These figures verify that the proposed bandwidth enhancement techniques are effective for handset Doherty PAs.

This paper outlines the use of a measurement based waveform CAD tool for enhanced PA design. Two measurement based models have been used to simulate a complete Doherty power amplifier together with output matching. The output matching network and auxiliary bias were optimised to produce a region of high efficiency typical of Doherty power amplifiers. Through the incorporation of a large signal de-embedding network, the current and voltage waveforms were accessed at the current generator plane. This allowed for the confirmation of Doherty operation on an individual device basis. This powerful tool allows for further optimisation of power amplifiers using well established waveform design procedures, previously not possible at high power levels.

This paper presents the first published transmission-line-based, high output power, voltage-mode Doherty PA. It is an asymmetrical Doherty PA, exploiting three identical GaN transistors in a compact design. The concept is validated by designing a prototype operating at an fractional frequency from 1.7 to 2.3 GHz. The measurements of the prototype demonstrate a peak output power of 49 dBm, providing 9 to 10 dB efficiency backoff (BO) with at least 39 % power-added efficiency (PAE) at 39 dBm output power.

A new design procedure for wide band Doherty power amplifiers

This letter presents an approach to maximize the output power and efficiency of a Doherty power amplifier (PA). The conventional carrier PA having match, used in a symmetric Doherty PA, does not deliver the saturated high efficiency at the 6 dB back-off power but at the 5.5 dB back-off power due to the knee voltage effect. To solve the problem, the gate biases of the carrier and peaking PAs are adapted. The gate bias voltage of the carrier PA is optimized for a higher peak output power, delivering a 3 dB larger peak power at match. That of the peaking PA is also optimized to have the same peak power of the carrier PA. A Doherty PA with the concept is designed using a 45 W gallium nitride (GaN) high electron mobility transistors (HEMT) for the carrier and peaking cells at 1.94 GHz. The measured average output power, drain/power-added efficiencies and gain are 44.35 dBm, 60.5/57.2%, and 12.75 dB for a 10 MHz long term evolution (LTE) signal with a 6.5 dB peak-to-average power ratio (PAPR).

Метою даної роботи є побудова еквівалентних електричних схем оптоелектронного навантаження, яке живиться від фотоелемента та акумулятора. В роботі показано необхідність створення таких еквівалентних електричних схем, а саме при підключенні світлодіодів та напівпровідникових лазерів до сонячних фотоелементів, в якості джерела електричної енергії, та при використанні акумуляторів електроенергії. Показано, що еквівалентні електричні схеми витікають з фізичних явищ в напівпровідникових пристроях і рівнянь, які описують явища перетворення електричної енергії в світлову. Викладено різні еквівалентні схеми оптоелектронного навантаження. Показано, як просту так і найбільш узагальнену еквівалентні електричні схеми. Зокрема, показано еквівалентну схему акумулятора і спрощені схеми фотоелемента та оптоелектронного випромінювача світла, де в якості навантаження виступає світлодіод. Зазначено, що розвитком даної моделі є більш узагальнена еквівалентна електрична схема, де в якості оптоелектронного навантаження виступає напівпровідниковий інжекційний лазер. Розписані їх параметри та викладені рівняння для струмів та напруг. Також показано існування пасивних паразитних елементів в таких електричних схемах. Також показано, що в якості схеми заміщення фотоелемента, в спрощеній моделі, використано ідеальне джерело напруги та резистор з конденсатором. В подальшому, в узагальненій моделі, для більш широкого моделювання роботи фотоелемента, в якості схеми заміщення було використано ідеальне джерело струму та нелінійні пасивні елементи. Тобто, в результаті, було отримано узагальнену еквівалентну електричну схему акумулятора, підключеного до фотоелемента та оптоелектронного навантаження. Побудовано рівняння для струмів та напруг в отриманої схеми заміщення. Зроблено висновок. Бібл. 7, рис. 5.

Common-mode (CM) equivalent circuit plays a critical role in understanding noise propagation path and devising suitable measurement and mitigation schemes in industrial drives. A two phase CM equivalent circuit is commonly used for studying the electromagnetic interference (EMI) issues in three-phase brushless dc (BLdc) motor drives. Recent studies on SiC-fed high-voltage BLdc drives show that the mutual coupling between the floating and conducting phases also contributions to the CM noise. However, the impact of neglecting the floating phase in CM analysis is not quantified. Therefore, a comparative analysis of two-phase and three-phase CM equivalent circuits is presented in this paper considering high-voltage drives. Through experiments on a 310 V, 1.5 kV SiC-fed three-phase BLdc drive, it is shown that using a two-phase equivalent circuit will significant underestimate the CM noise.

Using equivalent circuit analysis, the dynamic behavior of ultrasonic wave propagation in solid metals is investigated in this study, particularly in Langevin vibrators clamped with a resonant amplifier to enlarge the vibrating magnitude. For piezoelectric static feature, the piezoceramic impedance and equivalent circuits were obtained for the parameter model of the vibrator via the impedance analyzer. To analyze piezoceramic dynamic feature, the characteristic of motional current relative to frequency response was measured under practical operating voltage for the vibrator. Both static and dynamic features of a piezoceramic vibrator were compared to realize the difference and to build the dynamic equivalent circuit. The vibration measurement module of optical fiber was also employed to detect the maximum displacement of a vibrator with a resonant amplifier. The measured results demonstrate that the resonant frequency is moved to the lower frequency band. The new equivalent circuit model is proposed to further match the dynamic response and the stepped horn increases the vibrating amplitude by about seven times. This is the more efficient mechanical output for a vibrator.

Circuit representation, experiment and analysis of parallel-cell triboelectric nanogenerator