Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes

Novel full-swing BiCMOS/BiNMOS logic circuits using bootstrapping in the pull-up section for low supply voltage down to 1 V are reported. These circuit configurations use noncomplementary BiCMOS technology. Simulations have shown that they outperform other BiCMOS circuits at low supply voltage using 0.35 /spl mu/m BiCMOS process. The delay and power dissipation of several NAND configurations have been compared. The new circuits offer delay reduction between 40 and 66% over CMOS in the range 1.2-3.3 V supply voltage. The minimum fanout at which the new circuits outperform CMOS gate is 5, which is lower than that of other gates particularly for sub-2.5 V operation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Predicting the effects of entrapped gas or vapor formation on surge is very important in design and operation of liquid pipelines. This paper identified the scenarios in which entrapped air and vapor formation need to be considered in pipeline operation and design. Useful modeling methods utilizing common liquid pipeline transient hydraulics software are provided. Validation of the presented methods was completed using experimental data from published literature. Examples are presented in showing the implementation of the provided modeling methods on real pipeline design scenarios. Finally, advantages and limitations of the presented methods was discussed. The methods presented in this paper enable pipeline operators and design engineers to properly estimate the complicated surge issues such as the influence of air bubble venting and column separation and collapse using commonly available single phase hydraulics tools. The operators and engineers will benefit from the provided methods in finding and validating reliable surge mitigation solutions and creating pipeline design with higher integrity level. The paper also presents the limitation of the methods and continuous improvements that can be achieved in the future.

Voltage scaling has been used as a prominent technique to improve energy efficiency in digital systems, scaling down supply voltage effects in quadratic reduction in energy consumption of the system. Reducing supply voltage induces timing errors in the system that are corrected through additional error detection and correction circuits. In this paper we are proposing voltage over-scaling based approximate operators for applications that can tolerate errors. We characterize the basic arithmetic operators using different operating triads (combination of supply voltage, body-biasing scheme and clock frequency) to generate models for approximate operators. Error-resilient applications can be mapped with the generated approximate operator models to achieve optimum trade-off between energy efficiency and error margin. Based on the dynamic speculation technique, best possible operating triad is chosen at runtime based on the user definable error tolerance margin of the application. In our experiments in 28nm FDSOI, we achieve maximum energy efficiency of 89% for basic operators like 8-bit and 16-bit adders at the cost of 20% Bit Error Rate (ratio of faulty bits over total bits) by operating them in near-threshold regime.

Slow light with electromagnetically induced transparency (EIT) in the core of optical fibre containing three-level atoms is investigated. The guided modes are treated in the weakly guiding approximation which renders the analysis into a manageable form. The transparency window and permittivity profile of the core due to the strong pump field in the EIT scheme is calculated. For a specific permittivity profile of the core due to EIT, the propagation constant of the weak signal field and spatial shape of fundamental guided mode are calculated by solving the vector wave equation using the finite difference method. It is found that the transparency window and slow light field can be controlled via the optical fibre parameters. The reduced group velocity of slow light in this configuration is useful for many technological applications such as optical memories, effective control of single photon fields, optical buffers and delay lines.

To continue with the scaling of high-performance transistors, alternate materials and device architectures are being explored as replacements for contemporary strained-silicon (s-Si) FinFETs. While III-V materials, such as In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As, offer higher electron mobilities and injection velocities than s-Si, emerging 2-D materials and nanowire (NW) device architectures promise better immunity to short-channel effects. In this paper, we present a detailed device-level performance comparison of s-Si, In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As, monolayer black phosphorus (BP), and WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based planar and multigate (Fin and NW) n-MOSFETs across three successive future technology nodes. The analysis incorporates both intrinsic device characteristics obtained from an advanced quantum mechanical simulation tool and the effect of nonidealities using a physics-based analytical model. The results indicate that 2-D materials, such as monolayer BP, offers higher ON currents than s-Si and In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As for planar device architectures. However, compared to modern s-Si and In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As Fin and NW FETs, monolayer BP and WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> double-gate MOSFETs are reported to offer lower ON currents due to the smaller footprint at scaled technology nodes.

Dynamic Voltage and Frequency Scaling (DVFS) technique requires accurate observation of critical path delay for robust operation under aggressive supply voltage scaling. Logic paths contain several types of logic gates and path delay have voltage dependences because different logic gates have different voltage dependences. However, it is not well investigated that how the voltage dependence of the path delay changes induced by process variation. This paper describes the effect of the process variation on the voltage dependence of path delay. Ring Oscillator circuits fabricated in 65-nm CMOS process are used for the evaluation and analysis of the process variation dependence of the voltage delay curves.

This brief shows the necessity of power consumption in a dynamic cross-coupled latch-based comparator. The proposed comparator is mainly designed using a cascading method that benefits in lowering power consumption as well as power delay product which is suitable to implement in EEG (Electroencephalogram) applications and in other cardiac IMD (Implantable Medical Devices). The latched comparator as analog to digital converter series a crucial function in terms of the amount of power consumed. This work presents a cascaded comparator circuit which is simulated at the CMOS technology node of 180nm using the Mentor Graphics Tool. The simulation result shows power dissipation 19.126$\mu$W at 0. 8V supply voltage and 19.19$\mu$W at 0. 6V supply voltage which is quite less as compared to the existing comparator circuits. In addition, the power delay product of the proposed comparator is 0. 383pJ when the supply voltage is 0. 8V, and it is 0.0384 when the supply voltage is 0. 6V.

In this paper, a comparative study of transistor based various adiabatic logic styles has been done thoroughly for the first time in the near-threshold regime. A uniform simulation environment is taken into consideration for exact results. To verify the workability of the adiabatic logic styles in the near threshold regime, extensive simulations have been done considering 22nm technology. The study is based on the effect of the supply voltage, temperature, and capacitive load on power dissipations in various logic styles. Notable changes in consumption of power and degradation of output waveforms at different stages have been observed among the diverse set of logic styles chosen for analysis. From the simulation results Efficient Charge Recovery Logic (ECRL) is found to be most efficient in near-threshold regime and perform without sacrificing noise immunity and driving ability and consuming least power.

Wax formation and deposition in crude oil pipelines pose a very significant challenge, such as flow restriction, increased cost of maintenance and potential shutdowns. The goals of this study are to reduce wax accumulation in the China National Petroleum Corporation-Niger Petroleum (CNPC-NP) pipeline network, which connects the Agadem oil fields to the SORAZ refinery, by optimizing critical operating conditions. The Reliability of Aspen HYSYS for analyzing wax behavior was validated by the simulation model that closely matched the real-world data, with a simulated flow rate of 182.49 m³/h with, only 0.27% higher than the actual 182 m³/h. The study suggested changing the operating condition using a genetic algorithm method of optimization, which indicates a slight increase in the pressure from 0.6 MPa to 0.65 MPa, while decreasing in temperature from 51°C to 48.5°C and a potential increase in the flow rate to 187.49 187.49 m³/h. Furthermore, the results of the optimization led to a decrease in wax thickness from 0.058 mm to 0.0409 mm, which indicated an improvement in pipeline operating conditions. Also, the economic analysis revealed, the total capital investment was roughly $3.3 million, and the annual operating expenses were estimated to be $2.4 million. The financial indicators include an Internal Rate of Return (IRR) of 9%, a Net Present Value (NPV) of $2.14 million and a Profitability Index (PI) of 1.99, all of which were higher than the IRR of the current CNPC-Niger Petroleum, which was 8%. The results show that the economic performance of the crude oil pipeline system can be improved, and wax formation risk can be effectively decreased by combining simulation-driven decision-making with strategic operational parameter adjustment.

As we approach the limits of traditional Moore’s-Law scaling, alternative computing techniques that consume energy more efficiently become attractive. Stochastic computing (SC), as a re-emerging computing technique, is a low-cost and error-tolerant alternative to conventional binary circuits in several important applications such as image processing and communications. SC allows a natural accuracy-energy tradeoff that has been exploited in the past. This article presents an accuracy-energy tradeoff technique for SC circuits that reduces their energy consumption with virtually no accuracy loss. To this end, we employ voltage or frequency scaling, which normally reduce energy consumption at the cost of timing errors. Then we show that due to their inherent error tolerance, SC circuits operate satisfactorily without significant accuracy loss even with aggressive scaling. This significantly improves their energy efficiency. In contrast, conventional binary circuits quickly fail as the supply voltage decreases. To find the most energy-efficient operating point of an SC circuit, we propose an error estimation method that allows us to quickly explore the circuit’s design space. The error estimation method is based on Markov chain and least-squares regression. Furthermore, we investigate opportunities to optimize SC circuits under such aggressive scaling. We find that logical and physical design techniques can be combined to significantly expand the already-powerful accuracy-energy tradeoff possibilities of SC. In particular, we demonstrate that careful adjustment of path delays can lead to significant error reduction under voltage and frequency scaling. We perform buffer insertion and route detouring to achieve more balanced path delays. These techniques differ from conventional path-balancing techniques whose goal is to minimize power consumption by resizing the non-critical paths. The goal of our path-balancing approach is to increase error cancellation chances in voltage-/frequency-scaled SC circuits. Our circuit optimization comprehends the tradeoff between power overheads due to inserted buffers and wires versus the energy reduction from supply voltage downscaling enabled by more balanced path delays. Simulation results show that our optimized SC circuits can tolerate aggressive voltage scaling with no significant signal-to-noise ratio (SNR) degradation. In one example, a 40% supply voltage reduction (1V to 0.6V) on the SC circuit leads to 66% energy saving (20.7pJ to 6.9pJ) and makes it more efficient than its conventional binary counterpart. In the same example, a 100% frequency boosting (400ps to 200ps) of the optimized circuits leads to no significant SNR degradation. We also show that process variation and temperature variation have limited impact on optimized SC circuits. The error change is less than 5% when temperature changes by 100°C or process condition changes from worst case to best case.

Embedded systems account for wide range of applications. However, the design of such systems is faced with a diverse spectrum of criteria. The energy consumption, performance, and demanding security concerns are some of the most significant challenges in designing of such systems. With these challenges, the design process can be managed more easily if a flexible logic circuit with the ability of satisfying the above-mentioned concerns is taken into account. To achieve such a logic circuit, in this paper we have combined the sub-threshold operation and charge recovery techniques. Using our technique, lower power consumption, ability of operating at higher frequencies, and more security (to side channel attacks) than the existing logic circuits are achieved. This paper also presents an analytical proof about how sub-threshold charge recovery circuits can meet these characterizations. we have also confirmed our analytical discussions by examining our technique for full adder, and 8 × 8 carry-save multiplier in different frequencies, supply voltages, and CMOS technologies. Detailed SPICE simulations show significant improvements as compared to its existing counterparts in all simulated frequencies and supply voltages.

Wireless sensor network (WSN) is a highly-demanded application since the evolution of wireless generation which is often used in recent communication technology. A radio frequency (RF) transceiver in WSN should have a low power consumption to support long operating times of mobile devices. A down-conversion mixer is responsible for frequency translation in a receiver. By operating a down-conversion mixer at a low supply voltage, the power consumed by WSN receiver can be greatly reduced. This paper presents a development of low power CMOS mixer using forward body bias technique for wireless sensor network. The proposed mixer is implemented using CMOS 0.13 μm Silterra technology. The forward body bias technique is adopted to obtain low power consumption. The simulation results indicate that a low power consumption of 0.91 mW is achieved at 1.6 V supply voltage. Moreover, the conversion gain (CG) of 21.83 dB, the noise figure (NF) of 16.51 dB and the input-referred third-order intercept point (IIP3) of 8.0 dB at 2.4 GHz are obtained. The proposed mixer is suitable for wireless sensor network.

본 논문에서는 특별한 보정기법 없이 채널 간 오프셋 부정합 문제를 최소화한 2채널 time-interleaved (T-I ) 구조의 10비트 120MS/s 파이프라인 SAR ADC를 제안한다. 제안하는 ADC는 4비트-7비트 기반의 2단 파이프라인 구조 및 2채널 T-I 구조를 동시에 적용하여 전력소모를 최소화하면서 빠른 변환속도를 구현하였다. 채널 간에 비교기 및 잔류전압 증폭기 등 아날로그 회로를 공유함으로써 일반적인 T-I 구조에서 선형성을 제한하는 채널 간 오프셋 부정합 문제를 추가적인 보정기법 없이 최소화할 뿐만 아니라 전력소모 및 면적을 감소시켰다. 고속 동작을 위해 SAR 로직에는 범용 D 플립플롭 대신 TSPC D 플립플롭을 사용하여 SAR 로직에서의 지연시간을 최소화하면서 사용되는 트랜지스터의 수도 절반 수준으로 줄임으로써 전력소모 및 면적을 최소화하였다. 한편 제안하는 ADC는 기준전압 구동회로를 3가지로 분리하여, 4비트 및 7비트 기반의 SAR 동작, 잔류전압 증폭 등 서로 다른 스위칭 동작으로 인해 발생하는 기준전압 간섭 및 채널 간 이득 부정합 문제를 최소화하였다. 시제품 ADC는 고속 SAR 동작을 위한 높은 주파수의 클록을 온-칩 클록 생성회로를 통해 생성하였으며, 외부에서 duty cycle을 조절할 수 있도록 설계하였다. 시제품 ADC는 45nm CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 10비트 해상도에서 각각 최대 0.69LSB, 0.77LSB이며, 120MS/s 동작속도에서 동적 성능은 최대 50.9dB의 SNDR 및 59.7dB의 SFDR을 보여준다. 시제품 ADC의 칩 면적은 0.36mm2이며, 1.1V 전원전압에서 8.8mW의 전력을 소모한다.

SRAM used for the FPGA, requires higher stability and low power consumption. 8T SRAM cell has degraded write stability with the decreasing supply voltages. 10T SRAM cell has higher write stability because of the cut-off switch employed in the pull-up path in one of the inverters. The design of SRAM array with low power consumption and higher stability is of major importance. So, 1Kb SRAM array using 8T and 10T SRAM cells has been designed and compared for different design metrics. Write 0 and Write 1 power is lower by 1.98×, 3.52× in 10T SRAM Array than 8T SRAM Array at 0.9VDD, SS corner. Due to the usage of High-Vth transistors in 10T SRAM cell, the Read power is lower by 1.6× than 8T SRAM Array for 0.9V VDD at SS Corner. The leakage power while holding 0 is lower by 1.13× in 10T SRAM array than 8T SRAM array at FF corner at 0.9V VDD. The design metrics are evaluated for a wide range of supply voltage. The designs are implemented in Cadence Virtuoso in 45nm Technology node.

The increasing demand for high-performance two-stage CMOS Op-Amps in electronic, communications, and biomedical applications necessitates their operation with wide bandwidth, high voltage gain, and low power consumption. By leveraging the Bat Algorithm global search and local exploration capabilities, the study demonstrates a significant improvement in the amplifier’s overall performance. This design of a two-stage CMOS Op-Amp using 0.18 µm TSMC technology, powered by a ± 1.8 V supply voltage. The simulation outcomes were gathered using the PSPICE software (version 17.4). These design strategies prove highly efficient, achieving high gain, high frequency, and low power consumption. Additionally, the paper showcases the execution and simulation results of a two-stage CMOS Op-Amp based on the Bat Algorithm, utilising MATLAB for this purpose. The employment of the BA results in substantial enhancements in performance metrics. Specifically, the Unity Gain Bandwidth sees a doubling in its value, the voltage gain rises by 20%, power consumption falls by 39.1%, and the Common Mode Rejection Ratio improves by 20% compared to a two-stage CMOS Op-Amp designed without the BA. The findings underscore the BA potency as a robust optimisation method for boosting the performance of a two-stage CMOS Op-Amp.