Determining schedules for reducing power consumption using multiple supply voltages

Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert a Level Shifter (LS) circuit. As a penalty consequence, traditional LS circuits insert a delay and extra power consumption in the design. The dynamical behavior of MDSV designs has brought a new condition, where LS inserted in the circuit can be in an idle state temporally. This work presents a new architecture to reduce the power consumption and delay, bypassing the LS. The architecture explores an alternative path to current flow in the cases that LS is idle. With this new approach we reduce up to 15% of power consumption and up to 75% and 15% of delay.

Extensive research has proposed the use of multiple on-die power supplies (VDD) for reducing power consumption in CMOS circuits. We present a detailed study and design techniques for power delivery systems in dual VDD CMOS circuits. We first show that the total current to be delivered by the voltage supplies is significantly reduced (by 27%-46%) in dual VDD circuits. This current reduction prompts various design strategies that can be employed to design the power delivery system. We describe issues that arise at the system, board and package levels and propose a high-level model for the same. We then provide a new placement driven approach for designing on-die dual VDD power grids. Compared to already existing methods, the dual VDD grids generated by our approach reduce the worst case and average voltage drop by up to 12.3% and 6.8% respectively with no area overhead and sometimes improving wire congestion. We also show that dual VDD circuits can afford lower on-die decoupling capacitance budgets.

One of the biggest problems in complicated and high-performance SoC design is management of energy and/or power consumption. In this chapter, we present energy management techniques in system design including HW and SW, SoC architecture and logic design. Dynamic power consumption is the major factor of energy consumption in the current CMOS digital circuits. The dynamic power consumption is affected by supply voltage, load capacitance and switching activity. We present approaches to controlling supply voltage, load capacitance and switching activity dynamically and statically in system architecture and algorithm design levels. We also discuss about the memory architecture for reducing power and energy in HW and SW co-design of SoC. In the future CMOS technology, leakage power consumption becomes dominant, because the threshold voltages are scaled as the transistor size shrinks. We summarize the techniques for reducing leakage power in system architecture design. The contents of the chapter include the following issues; (1) power and energy consumptions in SoC design, (2) tradeoff between energy and performance, (3) tradeoff among energy, QoS (i.e., latency and computational precision), reliability, and flexibility (4) techniques for reducing dynamic power consumption, and (5) leakage power reduction techniques

In todaypsilas technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. It is therefore important to consider all abstraction levels to reduce this power. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Both the dynamic and static power consumption is evaluated for bit-parallel and bit-serial arithmetic. Simulations are done in a typical 130 nm technology. With only a minor cost in dynamic power consumption, a static power reduction up to 13 times is shown by using bit-serial arithmetic.

This chapter discusses design methodologies for ultra-low-power (ULP) CMOS circuits at different abstraction levels, namely system, architectural, logic, design, and layout. The main techniques to reduce power consumption are introduced such as reduction of circuit activity, operating frequency, switched capacitances and supply voltages. Low-voltage and low-power techniques for microprocessors are reviewed, including cache and interleaved memories. Previous chapters have introduced ULP techniques and possibilities for advanced processes with extremely low supply and threshold voltages. This chapter exploits techniques to achieve ULP consumption without aggressively changing processes. Many opportunities for reducing power consumption at a given throughput are opened by appropriately combining the ULP techniques presented here.

Both the capacity and the complexity of modern FPGA devices increase rapidly. Also, it is common that battery-powered embedded systems are equipped with FPGA devices. Therefore, reducing the power consumption of FPGA devices has become a very crucial issue. Not only dynamic power consumption but also leakage power consumption increases as the feature size to manufacture FPGA devices shrinks. To reduce the power consumption of FPGA devices, carbon-nanotube field effect transistor (CNFET) has emerged as a promising candidate for replacing silicon metal oxide semiconductor field effect transistor (Si-MOSFET). In this paper, we propose an FPGA slice design based on CNFET technology, and compare the performance and the power consumption characteristics of the proposed design with the same design based on Si-MOSFET. From the performance evaluation, we learned that the proposed design showed up to 5000 times better power-delay product (PDP) than the Si-MOSFET design. Especially reduction in power consumption was truly significant.

The energy efficiency and power consumption are the two primary and major concerns in present emerging applications like miniaturized bio medical sensors, pace makers, multimedia processors, etc. The energy and power consumption may decreases by multiple ways. The multiple power supply voltage design is an efficient and dominant technique for the reduction of energy and power consumption at processor level. The multi core processors uses level shifters and this level shifter may become burden, when its own energy and power consumption is high, at the same time there is area overhead also. In this paper a high speed Energy efficient level shifter circuit is proposed that performs level up shifting & Level down shifting. The design is designed & simulated using 90nm model files. The proposed one is a unique design, is encompass a level shifter and provision for auto selection of type of shift (Level up/Level down). The proposed level shifter strength has study at signal frequency of 1 MHz, 500 KHz, and 100 KHz with a load capacitance variation from 10fF-60fF. The proposed design has an average delay of 2.8 ns & power consumption is 36.4 nW at 0.4V VIN and 0.18 ns & 16 nW at IV VTN.

A voltage reference circuit is an essential block of a system to generate various internal voltages. Since it consumes static power in standby modes, it plays an important role in energy management of battery-limited applications. The bandgap reference (BGR) has been a widely used approach since it provides a well-defined large value ($\sim 1.15\text{V}$) with strong immunity to process, supply and temperature changes. Recently proposed BGR approaches achieved a great reduction of power consumption by taking only complementary-to-absolute-temperature (CTAT) quantity from a PN junction while they obtained proportional-to-absolute-temperature (PTAT) quantity from alternative CMOS circuits such as a CTAT divider [1]or leakage-based two diodes [2, 3]. However, these BGR schemes are formed with multiple branches fed from a supply voltage above 1.4V and require power consumption of order larger than 10nW. To further reduce power consumption, threshold-based reference approaches with CMOS-only circuits have been proposed [4, 5]. However, generation of a practical voltage level by up-scaling of a threshold-based reference also causes an amplification of the uncertainty by the same factor. I addition, though [4]has successfully achieved sub-nW power consumption, the threshold voltage eventually suffers from a large sensitivity to process variation because the threshold voltage is affected by process and design parameters. To reduce the effect of process variation, [5]proposed a PMOS-only circuit. However, it requires a different body biasing for a threshold difference that is needed to generate a non-zero reference.

Multiple supply voltages are often utilized to decrease power dissipation in high performance integrated circuits. On-chip power distribution grids with multiple supply voltages are discussed in this paper. A power distribution grid with multiple supply voltages and multiple grounds is presented. The proposed power delivery scheme reduces power supply voltage drops as compared to conventional power distribution systems with dual supplies and a single ground by 17% on average (20% maximum). For an example power grid with decoupling capacitors placed between the power supply and ground, the proposed grid with multiple supply and multiple ground exhibits, respectively, 13% and 18% average performance improvement. The proposed power distribution grid can be an alternative to a single supply voltage and single ground power distribution system.

Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for the case of combinational designs. The problem is NP-hard in general. To address this problem in the case of synchronous sequential digital designs, one needs to move some registers while applying voltage scaling. Moving these registers shifts some computational elements from critical paths, and can be done by basic retiming. Integrating basic retiming and voltage scaling to address this NP-hard problem cannot in general be done in polynomial run-time. We propose to first apply a guided retiming and then to apply supply voltage scaling on the retimed design. We devise new polynomial time algorithms to realize this guided retiming, and the supply voltage scaling on the retimed design. Experimental results on known benchmarks have shown that the proposed approach can reduce dynamic power consumption by factors as high as 61% for single-phase designs with minimal clock period. Also, they have shown that it can solve optimally the problem, and produce converter-free designs with reduced dynamic power consumption. For large size circuits from ISCAS'89 benchmark suite, the proposed algorithms run in 15s-1h.

This paper presents the study of XNOR gate circuits and implementation of an improved version of groundless two-input XNOR gate. All the circuits are designed with the same design parameters for a valid comparison. Supply voltage and load capacitance are taken as 1V and 5fF, respectively. Simulation is done using Cadence Virtuoso with 90nm technology parameters. Detailed analysis is done regarding power consumption, propagation delay, power delay product, energy-delay product, and the number of transistors used for implementation. Improved version of groundless XNOR gate achieves up to 90.4% reduction in power consumption and 88.2% reduction in PDP. All other parameters are found to be improved with the new design except the area requirement. Moreover, the area required for an improved XNOR gate is less than the area requirement of CMOS based XNOR gate.

Shrinking feature sizes, reduced voltages, and higher transistor count of nano-scale silicon chips challenge designers in terms of performance, power consumption, and reliability. This paper investigates the effect of simultaneous use of dynamic voltage and frequency scaling (DVFS) and body biasing (BB) on power consumption, reliability, and performance. An analytical model of reliability as a function of body bias voltage, supply voltage, and frequency is proposed. We derive a three dimensional optimization problem by exploiting proposed reliability model in conjunction with power consumption and performance model. The resulting problem is solved using widely-used geometric optimization to identify optimal supply voltage and body bias voltage and then is validated using accurate simulation. Afterwards, it is demonstrated how joint energy-performance-reliability space optimization method can be used in an adaptive reliability-aware power management systems. Finally, we show that combined soft error aware BB and DVFS is capable of improving power consumption about 30% in comparison to reliability-aware DVFS only for the same level of reliability and performance constraints.

PVT-compensated low voltage LNA based on variable current source for low power applications

A fully power aware globally asynchronous locally synchronous network-on-chip circuit is presented in this paper. The circuit is arranged around an asynchronous network-on-chip providing a 17 Gbits/s throughput and automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each NoC units. The dynamic power consumption can be reduced up to a factor of 8 while the static power consumption is reduced by 2 decades in stand-by mode.