Development of a lead free chip scale package for wireless applications

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

In this paper describes the four challenges in thermal management in communication devices. Four challenges in the electronic packaging industry are challenges in the cooling of three dimensional packages, challenges resulting from thermally induced warpages, thermal challenges arising from spreading and interface resistances and thermal challenges in the implementation of lead free solder. In three dimensional packaging technologies are now emerging field, in which tremendous reduction size and weight of wireless handheld devices. Thermally induced warpage become one of the major concerns in the automated manufacturing and assembly of multilayered PWBs. One of the big challenge in electronic packaging industry is to implement lead free solder alloy. Tin/silver/copper alloys are introduced as lead free solder in packaging.

Packaging technologies such as fan out wafer level packaging (FOWLP) and embedded chip in substrate technologies have gained a lot of attention recently from OEMs, OSATS, technology developers, and technology integrators in the integrated circuit (IC) industry as schemes for continuing wafer level chip scale package (WLCSP). Both technologies are focused on incorporating ICs into their packaging platform and on taking advantage of current process recipes and infrastructure as much as possible. However, by virtue of the new process steps and technologies required to get to 3-D packaged materials, such as through silicon vias (TSVs), wafer thinning and handling processes and requirements for alternative dielectric materials, many opportunities have arisen. Expectations are that many devices that follow a flip chip ball grid array (FCBGA) flow or WLCSP will adopt an embedded technology strategy for future generations. FOWLP has several advantages, over FCBGA and WLCSP including potential for system in package (SIP) configurations and 3-D integration, the ability to overcome pad limitation issues, and shorter interconnections and so higher electrical performance. However, to gain these advantages, requirements for processing will change due to the significant demands imposed on the materials used as permanent dielectric layers and the photoresists used in the fabrication processes. Cleaning chemistry must be designed to remove challenging films such as photoresists and residues created during other process steps; yet preserve the exposed metals such as the bond pads and Cu redistribution lines, as well as the permanent dielectrics. Device reliability and performance is heavily dependent on the proper working of all these components. The focus of this paper is to identify a manufacturable and reliable process and process window for removal of positive photoresists and residues in formation of under bump metallization (UBM) and contact pads in wafer level packaging (WLP). Our objective is to discuss a proven process that has been successfully implemented into a manufacturing environment. It has improved robustness and reliability over past-used solutions due to decreased sensitivity to moisture contamination, a significant cause of defects in many device applications.

Nonmagnetic Ni(V) metal and low consumption rate with solders are the advantages of sputtered Ti/Ni(V)/Cu under bump metallization (UBM). However, a Sn-rich phase (“Sn-patch” herein) can form in the Ni(V) layer after reflow and aging. In lead-free solder, Sn-patches form and grow more quickly than in Sn-Pb solder. Thus, the effect of Sn-patches on solder joint reliability becomes critical. In this study, Sn-3.0Ag-0.5Cu solder was reflowed with Ti/Ni(V)/Cu UBM at 250°C for 60 s, and then aged at 150°C for various durations. A high-speed impact test was introduced to evaluate solder joint reliability. After impact testing, it was found that, the larger the Sn-patch, the greater the propensity of the solder joint to suffer brittle fracture. The correlation between Sn-patch and solder joint reliability is discussed.

The interface microstructure interaction between SnCuAg Pb-free solder and three different Ni-based alloys under bump metallization (UBM) systems are studied using transmission electron microscopy (TEM). Ni reacts with Sn-rich Pb-free solder swiftly and is consumed readily by Pb-free solder. Thermally stable intermetallic compounds at the solder/UBM interface such as Cu/sub 6/Sn/sub 5/ or Ni/sub 3/P are necessary to protect Ni from being penetrated by Pb-free solders. Interface microstructure study reveals the potential process and reliability issues when applying Pb-free solders on existing UBM systems. Cu/Ni(V)/Al, can be used for Pb-free solder with marginal thermal budget. Au/Ni(V)/Ti/Al, is not suitable for Pb-free solder. And Au/eNi(P)/Al, is the most suitable for Pb-free solder and shows best thermal stability.

Current industry trends in the microelectronics packaging is going towards increasing in I/O density and small size packaging. Common use of solder material in packaging are the lead free solders. The popular lead free alloys include the SnAgCu (SAC) family such as SAC 305 and SC405. SAC solder alloys are favor due to high stains rate transient load and reliable operation at high temperature. Hence, it is suitable for application such as military application, avionics, and automotive [1], [2]. SAC alloy is frequently used in Wafer Level Chip Scale Package designs but achieving board level reliability especially when footprint go beyond a certain size causes challenge for SAC solder ball [3]. To overcome this issues, new type of solder alloy, SACQ and QSAC, has been established in current market to improve board level reliability performance. In this paper, studies of the 2nd level solder joint of the SAC305, SAC-Q and QSAC solder ball in terms of ball shear strength measurement at time zero and its failure mode will be shared. The SAC305, SACQ and QSAC solder alloys are also subjected to High Temperature storage (HTS) at 150°C for up to 1000hrs. The different IMC layers and the IMC growth will be investigated in this work. In this paper, studies of the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> level solder joint of the SAC305, SAC-Q and QSAC solder ball in terms of ball shear strength measurement at time zero and its failure mode will be shared. The SAC305, SACQ and QSAC solder alloys are also subjected to High Temperature storage (HTS) at 150°C for up to 1000hrs. The different IMC layers and the IMC growth will be investigated in this work.

Results from a joint US EPA and US electronics industry-funded life-cycle assessment of lead and two lead-free alternative solders are presented. Impact scores are reported in 16 different environmental categories for wave soldering applications. Bar solders evaluated include tin-lead, tin-silver-copper, and tin-copper. Tin-lead solder was determined to have higher impact scores than the lead-free solders in four categories, while having lower impacts in five. The use/application stage was the dominant contributor to most impact categories, while upstream and end-of-life processes also made significant contributions to specific impact categories, depending on the solder. Sensitivity analyses of the effect of silver production as well as landfill leachate data are also presented.

Three lead-free solder bumps (Sn-0.7Cu, Sn-3.5Ag, Sn-4Ag-0.5Cu) were produced by stencil printing of type 6 and type 7 solder pastes on wafers having electroless Ni-P immersion Au (ENIG) under bump metallization (UBM). The diameter and height of the solder bumps were measured to be 47 and 43 µm, respectively. Ball shear tests were carried out to evaluate the UBM solderability and the bonding quality of the solder bumps after 1 Reflow, multiple reflows and thermal aging at 150oC. The fracture surface, cross section microstructure and interfacial intermetallic compounds (IMCs) growth kinetics were investigated to identify the correlation between failure mode and the metallurgical characteristics of the UBM/solder interface IMC layers. The interfacial IMC phase was mainly (CuNi)6Sn5 for Sn-4Ag-0.5Cu and Sn-0.7Cu solders and Ni3Sn4 for Sn-3.5Ag solder. The coarsening of Ni3Sn4 IMC phase for Sn-3.5Ag solder was much greater than that of (CuNi)6Sn5 for Sn-0.7Cu and Sn-4Ag-0.5Cu solders with increasing reflows (solid/liquid reaction time). Even if only a small amount of Cu (0.5~0.7 wt %) is presented at the interface during reaction, the type, morphology and evolution of the interfacial IMC particles are greatly different. The growth kinetics of the interfacial IMC layers and the consumption of Ni-P UBM were also identified. Plate-like Ag3Sn phase with a rectangle shape was found in both Sn-4Ag-0.5Cu and Sn-3.5Ag solder bumps. The re-deposition of AuSn4 at the IMC/solder interfaces were observed for all of the solders after aging at 150oC for 1000 h. The failure mechanisms of the solder bumps were identified and analyzed. The morphology, size and chemical nature of the interfacial IMCs play a very important role on the reliability of the ultra fine pitch flip chip interconnects. P-enriched layer (Ni3P) underneath the interfacial Ni3Sn4 for Sn-3.5Ag solder was a weak interface, along which the failures were prone to occur.

There is considerable reported evidence that a large percentage of failures which afflict portable electronic products are due to impact or shock during use. Failures of the external housing, internal electronic components, package-to-board interconnects, and liquid crystal display panels may occur as the result of accidental drops. Moreover, the introduction of lead-free solder to the electronics industry will bring additional design implications for future generations of mobile electronic systems. In this paper, drop tests performed on PCBs populated with ball grid arrays (BGAs) are reported. During testing, measurements from strain gages were recorded using a high-speed data acquisition system. Electrical continuity through each package was monitored during the impact event in order to detect failure of package-to-board interconnects. Life distributions were established for both a lead-free and a tin-lead solder for various drop heights. In addition, failure analysis was carried out using microsection techniques, scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS). Resistance measurements throughout the drop event indicated that different failure mechanisms occurred for different drop heights. The explicit finite element (FE) method was employed to evaluate the peel stress at the critical solder joint and a stress-life model is then established for the lead-free solder. The maximum peel stress location was found to match the location of failure initiation revealed from the failure analysis. It was also discovered that, for board level drop testing, that there is a considerable difference between the lead-free solder characteristic life and the tin-lead solder characteristic life.

We developed a highly reliable fan-out-type chip scale package (CSP) for a microcomputer or an ASIC (Application Specific IC) . We found that the solder joint reliability of the CSP under temperature cycling is equal to that of a quad flat package (QFP) and that its mechanical strength (determined from a board-bending test) is much higher than that of a QFP. The fatigue life of a Sn-Ag-Cu lead-free CSP solder joint determined from a cyclic board-bending test is almost equal to that of a Sn-37Pb CSP solder joint. Moreover, compared to a QFP, the occupied area of a CSP is decreased by 75% and its weight is decreased by 90%.

To enhance the ability of lead-free solder joint to resist failures induced by mechanical impact and shock, some researchers have introduced low-Ag lead-free solder. In this study, the formation and evolution of IMC, the fracture morphology and performance of solder joint between SAC 105 solder and Under Bump Metallization (UBM) have been studied after different temperature storage aging and multi-reflow for WLCSP. The morphology and fracture surface of IMC have been analyzed by SEM, EDX and deeply etching techniques. The behavior of IMC and correlation with fracture mode of joint at high speed ball pull (HSBP) test has been investigated. It has been found that high temperature storage (HTS) aging results in IMC growing from one layer that is (Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> ) IMC to two different layers that are ((Cu,Ni) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> and (Cu,Ni) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> ). Multi-reflow results in the IMC layer thickness increasing a little and some needle-like IMC grain spalling into the solder.

The electromigration of flip chip solder joints is an ongoing reliability concern for manufacturers of integrated circuit (IC) components and electronic systems. As power levels of ICs continue to increase, current densities within individual solder bumps often increase, along with the operation temperatures of the die surface. Both of these factors have detrimental impact on the electromigration (EM) performance of the solder bumps, as they provide increased driving forces for the diffusion and dissolution of the under bump metallization (UBM) into the solder bumps. Additionally, these changes are occurring concurrently with the transition to Pb-free solder bumps for the next technology node. Compared to commonly used high-Pb bumps, Pb-free bumps typically have reduced lifetime with similar under bump metallization. In this study, a specially designed test vehicle was used to assess the EM performance of Pb-free solder bumps. Electroplated Sn2.6Ag solder bumps were tested with a variety of current density and temperature combinations. Lifetime data were collected for each of the conditions and a prediction model is established using Black's equation. The results were also compared with previous work done on high-Pb and eutectic SnPb bumps using the same test vehicle. From this work, Pb-free solder bumps are shown to have slightly decreased lifetime compared to high-Pb bumps, but still significantly higher than eutectic SnPb solder bumps. With the correct design strategies, including optimized via opening sizes and under bump metallization materials, SnAg Pb-free bumps can provide sufficient reliability for a majority of application conditions.

Interfacial reaction between Sn–Ag–Cu solder and Co–P films with various microstructures

The elimination of lead from solders for flip‐chip attachment has necessitated many new studies on the reliability of the resultant systems. There are many lead‐free solder material systems. However, most of them contain a large proportion of tin. The tin in the solder reacts with the copper layer present in some types of under bump metallisation (UBM) depleting the UBM of copper, and thereby causing loss of adhesion and a weak interface. In this work, the relative reliability of Cr/Cu/Cu and Cr/Cu/Cu/Ni UBM systems was studied. The UBM systems were deposited with an electroplated Sn‐3.5Ag lead‐free solder alloy. The results conclusively showed that the Cr/Cu/Cu/Ni UBM system is a better choice for the Sn‐3.5Ag lead‐free solder. In the Cr/Cu/Cu/Ni UBM system, the thickness of the nickel layer was found to be an important parameter. Multiple reflow and high temperature storage test results showed that serious depletion of the UBM layer could occur if the UBM layers were not optimised. The thermo‐mechanical reliability of Ni‐based UBM bumps showed promising results up to 1,500 temperature cycling.

The effects of lead-free solder paste (Sn3wt%Ag0.5wt%Cu) and lead-free solder ball (Sn4wt%Ag0.5wt%Cu) of a 1156- pin PBGA (plastic ball grid array) package on their solderjoint x-ray inspection are investigated. Emphasis is placed on the determination of the difference (shift) of the x-ray measurement parameters (e.g., solder diameter and solder thickness) between the lead-free and tin-lead (Sn37wt%Pb) solder joints. Also, the threshold adjustment values for the lead-free solder thickness, depending on the slice-location, are recommended and discussed.