Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

The design, demonstration and evaluation of a general purpose, field programmable smart pixel based photonic information processing system is presented. This novel architecture incorporates photoreceiver cells into a field programmable gate array (FPGA). Implemented with a photonic VLSI technology the device is suitable for prototyping photonic information processing systems. We report here on the photoreceiver design methodology and measure device performance.

The mitigation of single event upset (SEU) in SRAM based Field Programmable Gate Array (FPGA) is increasingly important as it is widely used in radiation environments such as space. As D flip-flop (DFF) and memory (including Block RAM and Configuration RAM) are the key elements in FPGAs, it is crucial to develop radiation hardening techniques for enhanced reliability of the DFF and memory. A novel hardened memory design for FPGA is proposed with multi-bit upset (MBU) protection. We further developed two prototype FPGA chips, one with and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13μm CMOS process and have a volume of 3 million equivalent logic gates. In contrast to the base FPGA, the SEU cross section of the memory in the hardened FPGA is at least three orders of magnitude lower. Also, no SEU upsets are observed in the DFF of the hardened FPGA.

The goal of this paper is to implement the secretion mechanism of the Thyroid Hormone (TH) based on bio-mathematical differential eqs. (DE) on an FPGA chip. Hardware Descriptive Language (HDL) is used to develop a behavioral model of the mechanism derived from the DE. The Thyroid Hormone secretion mechanism is simulated with the interaction of the related stimulating and inhibiting hormones. Synthesis of the simulation is done with the aid of CAD tools and downloaded on a Field Programmable Gate Arrays (FPGAs) Chip. The chip output shows identical behavior to that of the designed algorithm through simulation. It is concluded that the chip mimics the Thyroid Hormone secretion mechanism. The chip, operating in real-time, is computer-independent stand-alone system.

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two physical limitations: (1) The massive usage of routing multiplexers causes delay and power overheads as compared to ASICs. To reduce their power consumption, FPGAs have to operate at low supply voltage but sacrifice performance because the transistors drive degrade when working voltage decreases. (2) Using volatile memory technology forces FPGAs to lose configurations when powered off and to be reconfigured at each power Resistive Random Access Memories (RRAMs) have strong potentials in overcoming the physical limitations of conventional FPGAs. First of all, RRAMs grant FPGAs non-volatility, enabling FPGAs to be Normally powered off, Instantly powered on. Second, by combining functionality of memory and pass-gate logic in one unique device, RRAMs can greatly reduce area and delay of routing elements. Third, when RRAMs are embedded into datpaths, the performance of circuits can be independent from their working voltage, beyond the limitations of CMOS circuits. However, researches and development of RRAM-based FPGAs are in their infancy. Most of area and performance predictions were achieved without solid circuit-level simulations and sophisticated Computer Aided Design (CAD) tools, causing the predicted improvements to be less convincing. In this thesis,we present high-performance and low-power RRAM-based FPGAs fromtransistorlevel circuit designs to architecture-level optimizations and CAD tools, using theoretical analysis, industrial electrical simulators and novel CAD tools. We believe that this is the first systematic study in the field, covering: From a circuit design perspective, we propose efficient RRAM-based programming circuits and routing multiplexers through both theoretical analysis and electrical simulations. The proposed 4T(ransitor)1R(RAM) programming structure demonstrates significant improvements in programming current, when compared to most popular 2T1R programming structure. 4T1R-based routingmultiplexer designs are proposed by considering various physical design parasitics, such as intrinsic capacitance of RRAMs and wells doping organization. The proposed 4T1R-based multiplexers outperformbest CMOS implementations significantly in area, delay and power at both nominal and near-Vt regime. From a CAD perspective, we develop a generic FPGA architecture exploration tool, FPGASPICE, modeling a full FPGA fabric with SPICE and Verilog netlists. FPGA-SPICE provides different levels of testbenches and techniques to split large SPICE netlists, in order to obtain better trade-off between simulation time and accuracy. FPGA-SPICE can capture area and power characteristics of SRAM-based and RRAM-based FPGAs more accurately than the currently best analyticalmodels. From an architecture perspective, we propose architecture-level optimizations for RRAMbased FPGAs and quantify their minimumrequirements for RRAM devices. Compared to the best SRAM-based FPGAs, an optimized RRAM-based FPGA architecture brings significant reduction in area, delay and power respectively. In particular, RRAM-based FPGAs operating in the near-Vt regime demonstrate a 5x power improvement without delay overhead as compared to optimized SRAM-based FPGA operating at nominal working voltage.

The soft computing algorithms are being nowadays used for various multi input multi output complicated non linear control applications. This paper presented the development and implementation of back propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in programmable systems. For the neural network based instrument prototype in real time application. The conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGA have higher speed and smaller size for real time application than the VLSI design. The challenges are finding an architecture that minimizes the hardware cost, maximizing the performance, accuracy. The goal of this work is to realize the hardware implementation of neural network using FPGA. Digital system architecture is presented using Very High Speed Integrated Circuits Hardware Description Language (VHDL)and is implemented in FPGA chip. MATLAB ANN programming and tools are used for training the ANN. The trained weights are stored in different RAM, and is implemented in FPGA. The design was tested on a FPGA demo board. Keywords- Backpropagation, field programmable gate array (FPGA) hardware implementation, multilayer perceptron, pressure sensor, Xilinx FPGA.

This paper presents realization of a Delayed Cellular Neural Network (DCNN) on field programmable gate array (FPGA). The network has two cells and a strange attractor has been found in a system described by a differential equation. In the implementation stage, Xilinx System Generator (XSG) is used and discrete time model of the network is implemented on Xilinx Spartan 3e XC3S1600e FPGA development board. The realization of DCNN on FPGA chip provides an opportunity to make the system suitable for high operating frequency applications, such as secure communication and cryptographic systems.

In this paper, we introduce a new development system for creating real-time image processing hardware using custom computing machines with multiple Field Programmable Gate Array (FPGA) chips. Three distinct processes are accomplished within the development system: design entry, verification, and translation. A library of modules that implement common low-level machine vision functions is used to create complex designs based on a dataflow graph representation. The library's low-level image processing modules contain both gate-level and chip-level hardware components, of which the gate-level components are compiled into the functionality of available FPGA chips. Standard interfaces are established for input/output of the modules, allowing for the creation of sophisticated software support tools. Experimental results verify the utility of this development system for easily creating real-time machine vision hardware using multiple FPGA-based custom computing machines.

This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip.

Raman spectrometer has been widely used as an identification tool for analyzing material structure and composition in many fields. However, Raman scattering echo signal is very weak, about dozens of photons at most in one laser plus signal. Therefore, it is a great challenge to design a Raman spectrum data acquisition system which could accurately receive the weak echo signal. The system designed in this paper receives optical signals with the principle of photon counter and could detect single photon. The whole system consists of a photoelectric conversion module H7421-40 and a photo counting card including a field programmable gate array (FPGA) chip and a PCI9054 chip. The module H7421-40 including a PMT, an amplifier and a discriminator has high sensitivity on wavelength from 300nm to 720nm. The Center Wavelength is 580nm which is close to the excitation wavelength (532nm), QE 40% at peak wavelength, Count Sensitivity is 7.8*10⁵(S^-1PW^-1) and Count Linearity is 1.5MHZ. In FPGA chip, the functions are divided into three parts: parameter setting module, controlling module, data collection and storage module. All the commands, parameters and data are transmitted between FPGA and computer by PCI9054 chip through the PCI interface. The result of experiment shows that the Raman spectrum data acquisition system is reasonable and efficient. There are three primary advantages of the data acquisition system: the first one is the high sensitivity with single photon detection capability; the second one is the high integrated level which means all the operation could be done by the photo counting card; and the last one is the high expansion ability because of the smart reconfigurability of FPGA chip.

Modern Field Programmable Gate Arrays (FPGAs) posses small features, and have gained popularity in mission-critical systems. However, due to small FPGA features and harsh external conditions that can be faced by a mission-critical system, an FPGA chip can suffer from faults. This in turn raises the need to test an FPGA to ensure a reliable system performance. However, a mission-critical system requires that the test process should be non-intrusive, i.e., applications & FPGA regions that are not being tested remain unaffected. Hence, an online test scheme is required that not only verifies the correctness of an FPGA, but also does not degrade the performance of other, running FPGA applications. In this paper, we propose a Hardwired Network on Chip (HWNoC) as the Test Access Mechanism (TAM). Our online test scheme uses a HWNoC, to perform real-time streaming of test data that is non-intrusive to other communication traffic. Additionally, our online test scheme exhibits approx. 18 and 29 times lower spatial and temporal overheads as compared to existing schemes, respectively.

This paper presents a Field Programmable Gate Array (FPGA) -based platform for integrated multi-axis motion control and motor drive. As the development of FPGA, the integrated high-performance ARM processor on the FPGA has become the direction of FPGA development. This paper chooses the Xilinx Zynq-7020 programmable system-on-chip(SoC) which integrated dual-core ARM CPU and FPGA as a High-performance hardware platform. This platform is suits for the requirements of integrated multi-axis motion control and motor drive well, one ARM CUP completes the multi-axis position loop algorithm, speed loop algorithm and multi-axis trajectory generation, the other completes the human-computer interaction function. 4-axis current loop pipeline control and double sampling double updating current loop algorithm are accomplished by FPGA which can expand the current loop bandwidth and save FPGA logic resources. This platform’s architecture will improve the overall bandwidth of the system, achieve multi-axis synchronization accuracy at nanosecond level which makes position trajectory more accurate.

Current trends in computing require dedicated chips to speed up computing performances. These dedicated chips or ASICs are designed for specific applications, however, the drawback in this approach is that IC (Integrated Circuits) functionality cannot be changed. In areas where H/W programmability and reconfigurability is required, FPGA is the solution to achieve this. System on Chip (SOC) FPGAs (Field Programmable Gate Arrays) include processor hard blocks connected to fabric through various interconnects. This architecture provides better performance and the ability to run Operating Systems (OS) like Linux <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> that has direct access to programmable FPGA logic. This paper explains how to split the functions of an application code between hard block processor and FPGA fabric logic. OPUS is an open-source audio codec widely used in voice-over-IP (VoiP) applications. The codec execution can be accelerated by moving some of its functions to FPGA logic. One such function of OPUS code is implemented in FPGA logic using High-Level Synthesis (HLS). Shared DDR memory space is used to transfer the data between the processor and FPGA. In this paper, we summarize the reduction in execution time and processor load. The acceleration of OPUS codec allows processing of a greater number of audio channels in the SoC device compared to running the codec entirely on the processor.

The performances of System on Chip (SoC) and the Field Programmable Gate Array (FPGA) particularly, are increasing continually. Due to the growing complexity of modern embedded control systems, the need of more performance digital devices is evident. Recent FPGA technology makes it possible to include processor cores into the FPGA chip, which ensures more flexibility for digital controllers. Indeed, greater functionality of hardware and system software, Real-Time (RT) platforms and distributed subsystems are demanded. In this chapter, a design concept of FPGA based controller with Hardware/Software (Hw/Sw) codesign is proposed. It is applied for electrical machine drives. There are discussed different MultiProcessor SoC (MPSoC) architectures with Hw peripherals for the implementation on FPGA-based embedded processor cores. Hw accelerators are considered in the design to enhance the controller speed performance and reduce power consumption. Test and validation of this control system are performed on a RT motor emulator implemented on the same FPGA. Experimental results, carried on a real prototyping platform, are given in order to analyze the performance and efficiency of discussed architecture designs helping to support hard RT constraints.Request access from your librarian to read this chapter's full text.

With the continuous development of The Times and technology, artificial intelligence algorithm and AI technology based on Field Programmable Gate Array (FPGA) technology have been widely used in people's life. This paper introduces the extensive application of artificial intelligence technology in production and life in recent years and its challenges. In view of the complexity of AI algorithm operation, real-time requirements and fast update and iteration characteristics, this paper proposes that FPGA chip can better solve these problems. This paper introduces the working principle of FPGA chip to realize digital processing and other hardware resources in detail, and analyzes the application advantages of FPGA in AI industry, life, and engineering. Compared with other chips, FPGA has the characteristics of low cost and flexible implementation of new algorithms, to achieve the balance between performance and cost. Finally, this paper summarizes the advantages of FPGA compared with other chips, and puts forward the possible development way and development platform in the future.

SUMMARYIn wireless communication, Viterbi decoding algorithm (VDA) is the one of most popular channel decoding algorithms, which is widely used in WLAN, WiMAX, or 3G communications. However, the throughput of Viterbi decoder is constrained by the convolutional characteristic. Recently, the three‐point VDA (TVDA) was proposed to solve this problem. In TVDA, the whole procedure can be divided into three phases, the forward, trace‐back, and decoding phases. In this paper, we analyze the parallelism of TVDA and propose parallel TVDA on the multi‐core CPU, graphics processing unit (GPU), and field programmable gate array (FPGA). We demonstrate approaches that fully exploit its performance potential on CPU, GPU, and FPGA computing platforms. For CPU platforms, we perform two optimization methods, single instruction multiple data and multithreading to gain over 145 × speedup over the naive CPU version on a quad‐core CPU platform. For GPU platforms, we propose the combination of cached memory optimization, coalesced global memory accesses, codeword packing scheme, and asynchronous data transition, achieving the throughput of 404.65 Mbps and 12 × speedup over initial GPU versions on an NVIDIA GeForce GTX580 card and 7 × speedup over Intel quad‐core CPU i5‐2300, under the same manufacturing year and both with fully optimized schemes. In addition, for FPGA platforms, we customize a radix‐4 pipelined architecture for the TVDA in a 45‐nm FPGA chip from Xilinx (XC6VLX760). Under 209.15‐MHz clock rate, it achieves a throughput of 418.30 Mbps. Finally, we also discuss the performance evaluation and efficiency comparison of different flexible architectures for real‐time Viterbi decoding in terms of the decoding throughput, power consumption, optimization schemes, programming costs, and price costs.Copyright © 2013 John Wiley &amp; Sons, Ltd.