Development of Ball Grid Array Packages with Improved Thermal Performance

The trend towards ultra-miniaturization, high interconnection densities with minimal power consumption at low cost is driving the need for large, thin, high-stiffness substrate technologies. Glass substrates have emerged as a promising alternative to organic and silicon interposer packages due to their tunable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability. This paper presents a comprehensive study of the effect of glass CTE on board-level reliability of 100µm-thick glass ball grid array (BGA) packages, 18.5 mm x 18.5 mm in body size, with considerations of yield, warpage and thermal cycling performance. Polymer collars and novel doped solder alloys were also introduced to further enhance board-level reliability, and subsequently demonstrate the extendibility of direct SMT assembly of glass BGA packages to even larger body sizes. The test vehicle used in this study was an emulator of a single-chip application processor package. Daisy chain test dies, 10mm x 10mm in size and 100-200µm in thickness, were assembled onto the fabricated glass substrates with Si-matching CTE (3.8ppm/K) and board-matching CTE (9.8ppm/K) by dip-flux thermo-compression bonding with capillary underfill, at panel level. A stencil-based paste printing process was developed and optimized for panel-level balling of the glass packages with 250µm BGA at 400µm pitch. Variations in solder alloys were considered, including standard SAC105 and SAC305 used as reference, and the novel Mn-doped SACm by Indium Corporation. After singulation by laser dicing, the glass packages were finally mounted on mother boards by standard SMT reflow, after optimization of the heating profile to minimize solder voiding. Board-level yield was evaluated to 91%, and explained based on Shadow-Moire warpage measurements, showing a strong dependence to the chip-level underfill fillet size. Initial thermal cycling reliability was conducted on the glass BGA packages with and without polymer collars. All samples passed 600 cycles with stable daisy chain resistances, regardless of the glass CTE and solder alloy composition.

The current plastic Ball Grid Array (BGA) package has some disadvantages such as low level of solder crack resistance, large package warpage, and low cost performance at molding. In this paper, the author examined the improvement of the solder crack resistance, warpage and cost performance for a BGA. Firstly, solder crack resistance: as the author examined various combinations of materials used for the BGA package (molding compounds, die attach paste, and substates), it became clear that the molding compound is the most important factor for improvement of solder crack resistance. Also the molding compound factors which are necessary to withstand JEDEC level 2 treatment can be conjectured as the result of analysis of water absorption of the BGA package. Secondly, warpage: the author estimated warpage of a BGA when low Tg (below 175/spl deg/C) molding compound is used. In case of high Tg (about 180 to 200/spl deg/C) molding compound warpage can be calculated by an ideal elastic model. However, in case of low Tg it was clear that the visco-elasticity model of a polymer network is important for calculation. Thirdly, the cost performance of molding: a molding compound that can satisfy all of a plasma processing-less, short-cycle time (cure time 60 seconds), and post-cure-less for the improvement of cost performance, was examined. However, it seems difficult to satisfy all of the above items with a compound due to the problem of decrease of adhesion strength between the molding compound and the solder resist, at present.

Power integrity (PI) is among the main concerns in the design process of multilayer packages and printed circuit boards (PCBs). Based on Transmission Matrix Method (TMM), the PI performance of a Ball grid array (BGA) package mounted on a PCB is investigated in this paper. The power/ground planes and the power/ground balls on a PCB and package are entirely equivalent to distributed RLGC circuits model and co-analyzed. From this model, power performance could be computed with high efficiency. Moreover, a design rule of power/ground balls arrangement is obtained by reducing the equivalent inductance and equivalent capacitance of BGA for good power integrity performance.

This work researched the opportunity of application of aluminum thermomigration technology for fabrication of silicon packages. The thermomigration process is also called temperature gradient zone melting. The process was used for production of through-wafer interconnections. We describe both the process and the apparatus designed for making recrystallized doped regions during heating of a silicon wafer under a temperature gradient created along the wafer thickness. In addition, we also consider three types packages which would be possible to be made by aluminum thermomigration technology: ordinary silicon ball grid array (BGA) package, combined silicon BGA package and silicon-and-silicon BGA package.

With the development of low-K nanometer devices, the need for compatible packaging material is ever increasing. Liquid crystal polymer (LCP) is emerging as a promising material for RF, microwave, and millimeter-wave packaging. Its coefficient of thermal expansion can be matched to that of low-K die to ensure mechanical reliability. This paper, for the first time, characterizes the electrical performance of a wire bonded application-specific integrated circuit (ASIC) ball grid array (BGA) package based on LCP substrate technology for application in 10 Gb/s small form factor pluggable module (XFP) optical communication systems. Specifically, it compares the electrical performance of LCP to that of traditionally used FR4/spl I.bar/epoxy (FR-4) and Polyimide (PI) substrate materials. Findings show that at 10 GHz, insertion loss was decreased as much as 31% and 15% compared to FR-4 and PI, respectively. In particular, mode conversion was decreased by 66% and 42% compared to FR-4 and PI, respectively. Time delay was decreased by 10 and 4 ps compared to FR-4 and PI. No significant differences in power, ground coupling, and simultaneously switching output (SSO) noise at 10 GHz were observed. Based on the package structure used in this study, it was concluded that LCP offers superior electrical performance compared to FR/spl I.bar/4, PI, and is qualified as next generation substrate material for high data rate XFP BGA packaging.

The delivery time of a semiconductor packaging product has developed in a very short time period due to the demanding of 3C electronics. It is a fact that liability test of an electronic package takes much time and cost, and is a key issue in delivery time for advanced electronic packages. Recently, BGA packages using SnPb alloy are popular because of its advantage of mechanical stability and good solder ability. However, lead related materials can cause hazer to human health and environmental pollution thus Union has started to implement regulations such as WEEE and RoHS to limit the amount of electrical and electronic waste materials contain toxic substances and restrict the use of lead related materials. Today lead-free solder using Sn/Ag/Cu has been developed and implanted in ball grid array (BGA) packages, and specific liability tests for this new materials are required before delivery to the market. Since thermal cycling test (TCT) is a necessary testing with time consuming that can cause delay of the products to the market. We present the evaluation of the shear strength of the solder ball with various testing parameters such as temperature different, dwell time, and cycle times in TCT, and to formulate the.

A nonlinear finite element analysis was carried out to investigate the viscoplastic deformation of solder joints in a ball grid array (BGA) package under temperature cycling. The effects of constraint on print circuit board (PCB) and stiffness of substrate on the deformation behaviour of the solder joints were also studied The results indicated that high inelastic strain was developed in the joints close to the package center. On the other hand, high constraint was associated with the joint closest to the edge of the silicon chip. Increasing external constraint on the PCB caused a slight increase in stress triaxiality in the joint closest to the edge of silicon chip. There was an increase of inelastic strain in the solder joints with increasing the Young's modulus of the substrate.

Packages with multiple die provide additional challenges when documenting their thermal performance. To explore the thermal performance of multi-chip packages, stacked die configurations were chosen with the die stacked upon each other. A plastic ball grid array package (PBGA) was thermally tested with three die configurations. The thermal performance of the package was determined using the JEDEC 51 specifications. The package was also simulated using a finite element simulation to better illustrate the package performance. In addition, the validity of the superposition technique was evaluated in the determination of junction temperatures with change in power of the various die

Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic Ball Grid Array (BGA) packages. IBM has developed both Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packages which cover a wide range of package I/O capabilities required for high-performance devices, typically between 300 to more than 1600 I/O. Recently, there has been a lot of interest in Pb-free solders to replace typical Pb-based solders such as eutectic Sn-Pb used for balls in plastic BGAs (PBGA) for their assembly. The common feature of all proposed Pb-free solder alloys to date is that they are all Sn-based solders with the wt.% of Sn in the alloy typically greater than 90%. Antimony-based lead-free solders have been considered, but recently there has been a concern over the use of antimony (Sb) as well. The leading antimony-free (Sb-free) solder that has emerged from various Pb-free solder evaluations by industry and academic consortia at present is: 95.5Sn/3.8Ag/0.7Cu (SAC). The primary issues with changing from high-Pb based solders that are used in BGA assembly to electronic cards are: (1) wettability of the Pb-free solders to both Ni/Au I/O pads typically used in ceramic BGAs and card lands (Cu or Cu tinned with solder paste) with water soluble or no-clean fluxes; (2) the rate of intermetallic growth and its structure, with much higher Sn containing Pb-free solders; and (3) thermal fatigue reliability of the CBGA joints to organic cards. In this paper, initial assessment of a few leading Pb-free solders regarding wettability, microstructure and thermal fatigue life for CBGA applications is presented.

A surface‐mount bowtie antenna element with a ball grid array (BGA) packaging is proposed. Compared to a two‐dimensional end‐fire antenna, the proposed surface‐mount antenna element is a discrete three‐dimensional structure for obtaining a broadside radiation pattern. The proposed antenna element is mounted on the motherboard and fed by the balun located at the bottom layer of the motherboard to obtain a wide impedance bandwidth. In addition, the proposed antenna with the BGA packaging provides a cost‐effective solution for integration with surface‐mount devices on the same system board. The performance of the antenna prototype was verified by measurements.

The presence of discontinuities (e.g., vias, bends...) along a uniform signal path distorts the electromagnetic (EM) field pattern, resulting in signal integrity (SI) effects especially at RF/microwave frequencies. Such effects, which also arise when geometrical and material parameters of components in chips, packages and boards unexpectedly change during the fabrication process, may lead to a degradation of the system performance, if not accounted for at the genesis of the development process. In this work, we examine.the effects of discontinuities and technological fluctuations on the radio frequency (RF) performance of ball grid array (BGA) packages. For this purpose, an equivalent circuit model of the complete signal path' in a BGA package was developed for frequencies up to 25 GHz. The impact of multiple bends and vias on the signal quality was studied using this model. Furthermore, effects of up to 30% variation in material and geometrical parameters of each package component on its electrical characteristics and on the RF performance of the entire package were also critically investigated using the wideband package model. Based on the results of these investigations, design guidelines which can then be applied at the beginning of the development process to reduce cost and time, were deduced.

There has been a dramatic proliferation of research concerned with thermal stress in electronic package for the last three decades. Moreover, reviewing the mechanical bending during printed circuit board (PCB) assembly has become important in the reliability assessment of modern electronic systems. The primary research demonstrates that the assessment approach can be applied successfully to the design model of a ball grid array (BGA) package with a more complete and accurate assessment model for solder joint fatigue life under mechanical bending. Previous research has focused mostly on the thermal analysis in electronic packages; however, most modern portable electronic products used in mobile devices, personal digital assistants, and aircraft have to endure extreme environments that involve not only thermal but also mechanical bending conditions. Initially, mechanical bending tests were conducted to demonstrate the reliability of the electronic packaging during the manufacturing and shipping process. Currently, the microelectronic packaging faces mechanical bending when everyone uses his or her Smartphones. The mechanical bending occurs when the user touches the screen on the Smartphone. Therefore, interest in the mechanical bending of BGA packaging has increased with the uptake in mobile device use. In this research, the analytical solution and finite element analysis (FEA) are both presented to investigate the solder joint fatigue life. The analytical solution is presented for a PCB assembly subjected to mechanical bending by taking the axial stress, shear stress, and moment of the solder joints with discontinuity function into account. A FEM is proposed to analyze the solder joint fatigue life and to investigate the reliability of solder joints in BGA packaging subjected to mechanical bending.

Accelerated temperature cycling (ATC) was used to assess the thermal fatigue reliability of a Pb free, 37.5 mm fully populated, 1295 I/O ball grid array (BGA) package assembled with backward compatible or mixed alloy (Pb free BGA/SnPb paste) processing. The Pb-free BGA components were fabricated with Sn-4.0Ag-0.5Cu (SAC 405) solder balls. The surface mount assembly was done using several custom SnPb eutectic soldering profiles designed to produce different levels of Pb mixing in the BGA solder balls. The test program also included SAC405-SAC405 assemblies for reliability comparisons. The temperature cycling and metallographic data indicate that assembly parameters that produce the lowest level of Pb mixing degrade the solder joint fatigue reliability. Failure analysis demonstrates that the lower reliability is due to poorly formed solder joints resulting from incomplete reflow. The failed solder joints exhibit inadequate BGA ball collapse, minimal Pb mixing, and fatigue failure at the printed circuit board (PCB) side of the joints instead of the package-side fatigue failures that are typical for ATC testing. The test cells with more complete Pb mixing and the pure Pb-free test cell exhibited better fatigue reliability. However, failure analysis of these samples revealed that the data were compromised by the occurrence of a second failure mode in plated through hole vias that were incorporated into the PCB test vehicle. The presence of mixed mode failures (solder joint and via) precluded direct quantitative comparisons among all the test cells. The results are discussed within the context of previously published test results from the literature, including the impact of the contribution of via failures. Recommendations are outlined for additional testing to quantify the relationships between Pb mixing level and Pb-free reliability for this high density BGA package.

The development of high power and compact size semiconductor packages lead to the challenge in the need of high thermal dissipation design. For package level thermal solution, metal (especially copper) heat spreader and metal/metal-oxide filler thermal interface material are widely adopted. However, the thermal performance of packages is limited by isotropic conductive behavior of most of these materials. The thermal conducting performance could be further improved by directing the heat transportation in the direction desired, for instances the in-plane dissipation for heat spreader and the out-of-plane dissipation for thermal interface material. This present study reported the successful adoption of anisotropic thermal conductive pyrolytic graphite sheet as heat spreader and vertically aligned graphite sheet as thermal interface material in semiconductor package, individually. The Joint Electron Device Engineering Council standard still air junction to ambient measurement experiment shows that a flip chip ball grid array package incorporated with a pyrolytic graphite sheet as heat spreader improved thermal resistance of the module by 20%. The thermal dissipation behavior of the module was simulated with a well validated computational thermal dynamics model based on the experimental results. The anisotropic thermal conductive vertically aligned graphite sheet was also adopted as thermal interface material to replace the nowadays grease type thermal interface material. A thermal test chip assembled large size high performance flip chip ball grid array package mounted on a Joint Electron Device Engineering Council defined 4 layers thermal test printed circuit board was chosen as the test vehicle for thermal interface material performance test. The junction to case measurement experiment shows that the package with the anisotropic conductive thermal interface material improved the thermal resistance by 40%. Some novel designs were proposed basing on the application of this anisotropic thermal conductive material as validated by thermal simulation study. Package design guideline basing on the implementation of the anisotropic thermal conductive material will be discussed in this paper.

Refined simulation method and failure study of BGA package structure based on image drive