Digital predistorters sensitivity to delay alignment resolution

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), [Formula: see text]) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within “reasonably above” PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR [Formula: see text]50[Formula: see text]dBc, at 10[Formula: see text]W LTE modulated PA output, antenna point and PA output power of 39.5[Formula: see text]dBm.

We consider digital predistortion (DPD) for linearizing power amplifiers (PAs) of hybrid MIMO systems with subarrays. Designing such a DPD scheme is difficult because one DPD should linearize all PAs of a subarray whose beamforming coefficients are time-varying. We develop an adaptive DPD technique for each subarray based on direct learning method minimizing the sum of squared errors between the input and output signals of PAs. Use of the least mean square (LMS) Newton algorithm is proposed to adaptively control the DPD parameters. It is shown that the proposed DPD can simultaneously linearize multiple PAs in a subarray irrespective of its beamforming coefficients. Computer simulation results demonstrate that the proposed scheme can perform better than an alternative scheme that designs the DPD based on one of the PA outputs and uses the resulting DPD for all PAs of the subarray.

This paper investigates the trade-off between power amplifier (PA) nonlinearity, output power backoff (OBO), digital predistortion (DPD), and clipping and filtering (CF) in terms of energy consumption. The energy efficiency of a PA depends on the OBO of the signal and usually increases as the OBO decreases. Peak to average power ratio (PAPR) reduction methods like CF and PA linearization algorithms like DPD methods allow the use of a smaller OBO. Those algorithms show best results when used together. By studying the trade-off between the power consumed in the CF and DPD circuits versus having a larger OBO for a target bit-error rate (BER), we show that below a certain PA output power the power consumption is not reduced by decreasing the OBO. We also show that the increase in distortion noise when using DPD and CF might defeat the purpose of their use in terms of power consumption. Given the trend toward smaller cells like femtocells, requiring less output power, CF and DPD may not be required at all, leading to a simpler and power saving transmitter design.

Design of high-efficiency power amplifier (PA) is one of the key challenges to realize green radios, wherein digital predistortion (DPD) is deployed to reduce the PA’s power back-off and thus increase its power efficiency. As the bandwidth of the transmit signal increases, stringent requirements are posed on the DPD linearization performance with limited sampling rate and dynamic range for the analog-to-digital converter (ADC) in the DPD feedback channel. In this paper, under a fixed ADC sampling rate, novel DPD architecture is proposed to compensate for the PA nonlinearity with limited ADC dynamic range. In the feedback channel of the proposed architecture, an extra radio frequency (RF) cancellation chain is introduced to eliminate the linear component of the PA amplified signal, and thus the requirement on the ADC dynamic range can be significantly reduced. Subsequently, by accurately estimating the loop delay and attenuation of the cancellation chain, the baseband replica of the RF cancelling signal is recovered, and the original PA output signal is rebuilt to estimate the DPD coefficients. Finally, experiments show that for the long term evolution (LTE)-advanced signals, the proposed architecture can achieve an adjacent channel leakage ratio lower than −47.6 dBc, which outperforms the conventional DPD by about 3.4 dB, with the effective bits of the ADC being reduced by 4.4 and a power added efficiency of 43.8% with 7.3 dB power back-off being observed for a fabricated Doherty PA with 50-dBm saturation power.

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.

The application of digital predistortion in base band signal is an extended method of amplifier linearization to reduce the adjacent channel interference (ACI) in those systems in which a varying envelope modulation scheme like OFDM and MQAM is used. Digital baseband predistortion is a highly cost-effective way to linearize power amplifiers (PAs), but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W-OFDM), PA memory effects can no longer be ignored. In this paper we proposed a new technique for adaptation of digital predistorter that considers memory effects in power amplifiers. This method is a combination of two techniques, memory polynomial predistortion and slope-dependent method. This new technique is validated by using a 1.9 GHz 60W LDMOS power amplifier and various signals such as 2-carrier and 3-carrier CDMA.

In this paper, we evaluate the effect of applying peak-to-average power ratio (PAPR) reduction and digital pre-distortion (DPD) on two types of radio frequency power amplifiers when an orthogonal frequency division multiplexing (OFDM) signal is used. The power amplifiers under test are a standard class-AB amplifier and a Doherty amplifier. The PAPR reduction methods are based on a state-of-the art convex optimization formulation and on the standard clipping and filtering technique. The DPD method consists of modeling the behavior of the power amplifier using a parallel Hammerstein model, and then extracting the inverse parameters based on the indirect learning architecture. To achieve better DPD performance, extracting the DPD parameters based on multiple-step iterations is investigated. The cases where PAPR reduction and DPD are applied separately and combined are studied and investigated. Power amplifier figures of merit are evaluated. Good performance is shown when combining both pre-processing techniques up to a certain operating point where DPD performance deteriorates due to generation of strong peaks in the signal. In addition, a difference in the power amplifier behavior is reported and analyzed.

The inherent nonlinear behavior exhibited by power amplifiers (PAs) in saturation mode is a major impediment in wireless systems to achieve higher power efficiency, and higher spectral efficiency. Although PA behavioral modeling and digital predistortion (DPD) techniques are widely utilized at transmitter to characterize and linearize such distorted nonlinear output of PAs, the nonlinear distortions with memory effects have become more severe due to simultaneous strong crosstalk between multiple PA branches in multiple-input multiple-output (MIMO) arrays. Furthermore, current multi-input behavioral models suffer from a sharp increase in number of coefficients as the number of transmitter path increases in MIMO. In overcoming these challenges, we propose a decomposed cross-correlation based single-input-single-output (CC-SISO) behavioral modeling architecture. The proposed solution utilizes a low-cost, novel cross-correlation based method to estimate and cancel the simultaneous nonlinear and reverse crosstalk from multiple PA branches. Once the crosstalk is mitigated, the MIMO DPD can be implemented with single-input DPD blocks which significantly reduces the complexity. Furthermore, CC-SISO DPD eliminates the requirement for signal feedback paths before and after the PA, and thus reduces overall hardware implementation complexity. Through simulations, we demonstrate that the proposed CC-SISO architecture can reduce the overall complexity of state-of-art multi-input DPD models for MIMO systems.

Digital predistortion (DPD) exploiting the Volterra series can effectively compensate the strong nonlinearities (with memory effects) of power amplifiers. Diverse pruning schemes have been proposed to reduce the computational complexity with comparative performances. Regrettably, the mechanism of basis construction in different DPDs that is related to the complexity-efficiency tradeoff has not been well-studied. In order to compare methodically the Volterra-series based DPDs, the key parameters of the basis are studied here. Especially for the cross terms that describe the interaction between nonlinearities and memory effect, the complexity-efficiency tradeoff cannot be addressed directly. Thus, the basis construction of DPDs is firstly mapped to the general Volterra-series to observe the pruning property of each DPD. The diagonal dispersal property on basis construction is concluded as the most efficient and reliable way for pruning DPD techniques. The running complexity-accuracy tradeoff is quantitatively analyzed via the number of floating point operations. With the best performance settings found by the Qhull algorithm, the experimental results show that (1) the nonlinear order of the cross terms is more significant than the related memory depth, and (2) basis construction with diagonal dispersal properties effectively shows the complexity-efficiency tradeoff of different DPDs. These results offer new angles to assess the feasibility of DPDs and their involved complexity.

A novel approach for power amplifier (PA) characterization suitable for single iteration digital predistorter synthesis is proposed. This approach consists of synergetic crest factor reduction and baseband digital predistortion to avoid the average power variation at the input of the PA between the characterization and linearization steps. This is achieved by bypassing the crest factor reduction block during the characterization step and by applying it concurrently with digital predistortion in the linearization step. First, the PA's behavior sensitivity to the average input power is evaluated. The limitations of conventional approaches for the PA characterization, in the context of single iteration digital predistortion, are then demonstrated. The performance of the proposed technique is validated experimentally on a 300-W peak PA. The measured improvement of the adjacent channel power ratio at the output of the linearized amplifier is 16 dBc for the conventional approach and 29 dBc for the proposed approach.

The paper presents the results of laboratory studies on influence of DC transistor operating conditions both on power amplifier (PA) linearity and effectiveness of digital predistortion procedure. The impact of DC operating conditions of 10 W GaN HEMT power amplifier on nonlinearity factors without and with digital predistortion (DPD) were investigated. The obtained results show that there is an additional improvement in adjacent channel leakage ratio (ACLR) of the order of a few dB only by an increase in the quiescent drain current of PA transistor. However, some noticeable improvement of ACLR with significant increase in PA power added efficiency (PAE) is obtained for PA with digital predistortion.

This paper proposes a digital predistortion (DPD) technique to improve linearization performance when the power amplifier (PA) is driven near the saturation region. The PA is a non-linear device in general, and the nonlinear distortion becomes severer as the output power increases. However, the PA’s power efficiency increases as the PA output power increases. The nonlinearity results in spectral regrowth, which leads to adjacent channel interference, and degrades the transmit signal quality. According to our simulation, the linearization performance of DPD is degraded abruptly when the PA operates in its saturation region. To relieve this problem, we propose an improved DPD technique. The proposed technique performs on/off control of the adaptive algorithm based on the magnitude of the transmitted signal. Specifically, the adaptation normally works for small and medium signals while it stops for large signals. Therefore, harmful coefficient updates by saturated signals can be avoided. A computer simulation shows that the proposed method can improve the linearization performance compared with the conventional DPD method in highly driven PAs.

With the high interest in digital modulation techniques which are very sensitive to the PA nonlinearity, modern wireless communication systems require the usage of linearization techniques to improve the linear behavior of the RF power amplifier. The powerful and cheap digital processing technology makes the digital predistortion (DPD) a competitive candidate for the linearization of the PA. This thesis introduces the basic principle of DPD, its implementation on FPGA and the adaptive DPD system. The linearization of 4 PAs with DPD technique has been introduced: for the hybrid class AB PA operating at 2.6 GHz with a WiMAX testing signal, 33.7 dBm average power, 29.6 % drain efficiency, 13 dB ACPR and 9 dB NMSE improvement have been obtained; for the hybrid Doherty PA operating at 3.4 GHz with an I/Q testing signal, 35.0 dBm average power, 36.8 % drain efficiency, 12 dB ACPR and 13 dB NMSE improvement have been obtained; for the MMIC class AB PA operating at 7 GHz with an I/Q testing signal, 29.4 dBm average power, 25.7 % drain efficiency, 12 dB ACPR and 12 dB NMSE improvement have been obtained; for the two-stage PA operating at 24 GHz with an I/Q testing signal, 23.5 dBm average power, more than 14.0 % drain efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The DPD algorithm has been implemented on FPGA with two methods based on LUT and a direct structure with only adders and multipliers. The block RAM on the FPGA board is chosen as the table in the LUT methods. The linearization performance for these three methods is similar. The test PA is the hybrid Doherty PA mentioned above and the test signal is the I/Q signal with 7.4 dB PAPR. 35.1 dBm average power, 36.8 % efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The cost of logic resources for the direct structure method is the largest with 1,172 flip-flops, while the number of flip-flops for the two LUT methods are 263 and 583, respectively. A new adaptive algorithm has been proposed in this thesis for the adaptive DPD system. This new algorithm improves the performance in extracting the model parameters in complex number domain. With the experimental data from a combined class AB PA, the final accuracy of the model extracted by the new algorithm has been improved from -20 dB to about -40 dB and the converge speed is faster

The design of conventional digital predistortion (DPD) requires an analogue-to-digital converter (ADC) with a sampling frequency that is multiple times the signal bandwidth, which is extremely challenging for sub-Nyquist sampling systems with undersampled signals. To address this, this paper proposes a neural network (NN)-assisted wideband power amplifier (PA) DPD method for sub-Nyquist sampling systems, wherein a dual-stage architecture is designed to handle the ambiguity caused by subsampled communications signals. In the first stage, the time-delayed polynomial reconstruction method is employed to estimate the wideband DPD nonlinearity coarsely with the undersampled signals with limited pilots. In the second stage, an NN-based DPD method is proposed for the virtual training of the DPD, which learns the up-sampled DPD behavior by taking advantage of the pre-estimated DPD model and the input data signals, which reduces the length of the training sequence significantly and refines the DPD behavior efficiently. Simulation results demonstrate the efficacy of the proposed method in tackling the wideband PA nonlinearity and its ability to outperform the conventional method in terms of power spectrum, error vector magnitude, and bit error rate.

We consider the design of a digital predistortion (DPD) scheme when there is a crosstalk between a local oscillator (LO) and a power amplifier (PA) called LO self-coupling. We first develop a baseband equivalent model for a direct conversion transmitter afflicted by LO self-coupling. Based on this model, a two-stage process, consisting of a feedback equalizer (FBEQ) and DPD, is proposed for the joint compensation of PA nonlinearity and LO self-coupling. The advantage of the proposed DPD over conventional DPD is demonstrated through computer simulation.