Digital signal processing on a fully programmable platform

A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data streams (SIMD) and reconfigurable architecture. Equipped with eight SIMD-controlled 16-bit datapaths which can also be reconfigured as two 32-bit datapaths, the DSP core can process both 16-bit and 32-bit data in parallel, showing high performance, especially in the applications preferring parallel data flow computations, such as image processing. The SIMD scheme is extended with the instant-scalability of datapaths (ISSIMD), which offers the DSP a capability of dimension-controllable vector processing, so that to provide flexibility for different embedded applications. A first prototype in 0.18-/spl mu/m CMOS technology has been fabricated, which achieves IGMACS performance at the clock of 125 MHz.

In this paper, we describe the multiple biometric recognition system based on 32 bit floating-point digital signal processor (DSP) and field programmable gates array (FPGA). In addition, it has the function of real-time display, which can help the users easily capture the perfect image that they need. Different from other platforms of using DSP and FPGA, we have two kinds of parallel bus interfaces between them, the EMIF and HPI interface. With the help of the Hardware Description Language (HDL) Verilog HDL, we make it true that the DPS and FPGA can co-process the matching algorithms. Comparing with the matching time that processes only by the DSP, the co-processing is more efficient than the processing only by one processor. Besides, we leave several parallel and series interfaces in our board for the future use. Therefore, our system can be applied to many different digital signal processing domains and provide them an excellent computing platform.

An FPGA implementation of the matching pursuit algorithm for a compressed sensing enabled e-Health monitoring platform

This work presents the hardware and software architecture for the detection of fractures and edges in materials. While the detection method is based on the novel concept of Low Transient Pulse (LTP), the overall system implementation utilizes two microelectronics technologies: Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The DSP carries out the analysis of the received signal at a much lower rate hence can accommodate a large number of signal channels. The FPGA runs at a higher frequency (62.5MHz) to generate the LTP signal and to calculate the envelope of the received signal (sampled at 1MHz). This research elaborates on designing a Quadrature AM (QAM) demodulator on the FPGA for the received signal from the ultrasound and for the detection of the presence of edges/fracture on the test materials. The complete system is designed and optimized in a high level Matlab\Simulink fixed point simulation. Different sub-blocks are then implemented and optimized on the FPGA where efforts are taken to maintain its accuracy with the simulated model. In this work, the technology is applied to determine the location of the Sawbone plate edges based on the received signals which are then passed through a QAM demodulator in the FPGA and a peak detector in the DSP to calculate the echo peak times.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

Due to globalization of Integrated Circuit (IC) design flow, Intellectual Property (IP) cores have increasingly become susceptible to various hardware threats such as Trojan insertion, piracy, overbuilding etc. An IP core can be secured against these threats using functional obfuscation based security mechanism. This paper presents a functional obfuscation of digital signal processing (DSP) core for consumer electronics systems using a novel IP core locking block (ILB) logic that leverages the structure of flip-flops and combinational circuits. These ILBs perform the locking of the functionality of a DSP design and actuate the correct functionality only on application of a valid key sequence. In existing approaches so far, executing exhaustive trials are sufficient to extract the valid keys from an obfuscated design. However, proposed work is capable of hindering the extraction of valid keys even on exhaustive trials, unless successfully applied in the first attempt only. In other words, the proposed work drastically reduces the probability of obtaining valid key of a functionally obfuscated design in exhaustive trials. Experimental results indicate that the proposed approach achieves higher security and lower design overhead than previous works.

Low switching frequency is always used in an electric rail traction induction motor control system, in order to reduce switching losses and increase system reliability. But under low switching frequency, the conventional single pulse width modulation (PWM) technique for the whole speed region will produce a large number of harmonic components, which in turn cause motor heating, torque ripple, and other adverse effects. In this paper, a hybrid PWM technique formed by merging carrier-based asynchronous and synchronous modulation and optimal synchronous modulation is proposed to achieve low losses and total harmonics based on very low switching frequency. A simple low-cost and low-power digital signal processor (DSP) and field programmable gate array (FPGA) hybrid hardware structure is then adopted for implementing the technique, which fully utilizes advantages and resources of each processor. Total harmonic distortion of the system can hence be reduced by operating with the high-precision hybrid PWM, while not compromising the multirate and multitask processing requirements of traction control. Detailed implementations in both DSP and FPGA with high accuracy, low usage of resources, and computational burden are then described, focusing particularly at the smooth transitions among different PWM schemes. Simulations and experiments are eventually performed with results captured for validating the presented hybrid PWM technique.

A new built-in self-test (BIST) methodology is presented in which all generation and compaction functions are executed by basic building blocks such as adders, ALU's, and multipliers, performing regular arithmetic functions in digital signal processing (DSP) cores. It is demonstrated how these components are themselves tested, and subsequently used to perform more complex testing functions. The need for extra hardware is either entirely eliminated or drastically reduced, test vectors can be easily distributed to different modules of the system, test responses can be collected in parallel, and there is virtually no performance degradation. As an integral part of the proposed BIST environment, arithmetic two-dimensional (2-D) generators of pseudorandom test vectors are also introduced to further integrate the scheme with parallel scan and boundary scan designs used to test peripheral devices of the core.

Parameter interpolation is more capable of modern computer numerical control (CNC) than traditional linear/circular interpolation with higher speed and higher precision. Most of non-uniform rational B-spline (NURBS) interpolation algorithms were developed based on the chord error and machines capability, where interpolation points are calculated beforehand to overcome acceleration/deceleration (acc/dec) and jerk problem, which needs large memory. In this paper, a NURBS interpolator based on feedrate section is proposed. Instead of a single interpolation point, this interpolator aims to feedrate section, which makes it possible to run on a digital signal processor or field programmable gate array (FPGA) whose memory is limited. Experiment on FPGA showed the performance of interpolation. A mould experiment verifies the feasibility of application.

The pulse width modulation (PWM) is an important segment in power electronic inverters and multilevel inverters (MLIs) design. The space vector modulation (SVM) methods own distinct advantages over other PWM methods. However, MLI SVM has involved more mathematics in their executions. Hence, the digital signal processors (DSPs) or field programmable gate arrays (FPGAs) based digital implementations are highly preferred for MLI SVM realizations, which require exceptional properties. The conventional MLI SVMs use complex mathematical functions to solve their internal functions to identify the space vector diagram (SVD) sub-triangle and over modulation boundary switching on-times. Particularly these are the changes in the position of reference vector with respect to their sub-triangle positions involving higher mathematical functions. This paper proposes a simplified three-level MLI SVM that reduces the sub-triangle and over modulation switching on-time calculations with reduced mathematical functions. The proposed MLI SVM is derived based on two-level SVM without changing the reference vector position, unlike the traditional approaches. This helps in extending the SVM for any n-level inverter with additional LUTs. The detailed theoretical study, MATLAB-Simulink system generator simulations and Xilinx FPGA family SPARTAN-III-3A based experimental implementations are done with three-level neutral point MLI fed induction motor drive. The theoretical design, analysis, and experimentation results validate the advantages of the proposed PWM design and its implementation. In addition, the proposed implementation is executed from the MATLAB Xilinx system generator directly into target FPGA, which makes it faithful, efficient and minimizes the time spent.

This paper presents an approach for the mismatch pulse compression implementation in spread spectrum radars with binary phase intra-pulse modulated pulses. Design and verification of the matched and mismatched filter for signals coded by Barker and M sequences are accomplished on a digital radar signal synthesis and processing platform based on direct digital synthesis (DDS) and field programmable gates array (FPGA) technology. Coefficients of mismatched filters are obtained by DIRLS algorithm with 16-bit resolution. The compressors are verified with sequences lengths of 13 and 31, and bandwidth of 3.3 MHz.

Current legislation in European countries, as well as in other parts of the world, is putting stricter limits on pollutant emissions from road vehicles. This issue, in conjunction with the increase awareness of consumer for the environmental problems, will require the development of new clean propulsion systems in disruption with the current mobility solutions based on internal combustion engine. Electric, hybrid and fuel-cells vehicles (Chan, 2007) are now recognized as an indispensable mean to meet the challenges associated with sustainable mobility of people and goods. In this paradigm shift, the electric motor (EM) will assume a key role in the propulsion of future vehicles and, unlike vehicles based on internal combustion engines, the high energy and power densities will facilitate the development of new powertrains configurations. In particular, multi-motor configurations, where several EMs are allocated to each driven wheel of the vehicle, represent an attractive configuration for electric vehicles (EVs), due to the independent wheel torque control and the elimination of somemechanical systems, like the differential. These features, allied with the fast dynamics of EMs, are being explored to increase the vehicle maneuverability and safety (Geng et al., 2009) and improve the performance of the EV traction system (Hori, 2004). To cope with this rise in functional and computational complexity that current (and future) EVs require, in this work we explore the new Field-programmable Gate Array (FPGA) platform to address the powertrain control, i.e. involving the electric motor and the power converters control, of multi-motor EVs. In the past two decades, motor control applications have been dominated by software based solutions implemented in DSPs (Digital Signal Processors), due to the low cost and ease of programming (Cecati, 1999). However, these DSP solutions are facing increasing difficulties to respond to the ever-increasing computational, functional and timing specifications that modern industrial and vehicular applications require (Monmasson & Cirstea, 2007). For instance, when single-coreDSP based solutions needs to incorporate complex and time-critical functions, e.g. multi-motor control, the sequential processing of this approach decrease the controller bandwidth (see Fig. 1), which may compromise the application timing specification. Multi-core DSPs are a possible alternative to address this concern, but they also add costs and interconnection complexity. Consequently, in the last years, FPGAs received an increased interest by the academy and industry as an option to offload time-critical tasks from the DSPs (Lopez et al., 2008; Rahul et al., 2007; Ying-Yu & Hau-Jean, 1997), or even replace the DSPs control platform by a System on Chip (SOC) based on FPGAs (Idkhajine et al., 2009). 7

We present a novel detection system for nuclear magnetic resonance (NMR) logging tool with direct connection of receiver to low inductance antenna. The detection system contains receiver and signal acquisition circuit with high signal-to-noise ratio (SNR). The direct balanced connection of receiver to antenna increases SNR of the NMR signal. The first stage of receiver has a balanced input built on ultra low noise wideband operational amplifiers LMH6626. The maximum receiver gain is 105 dB and its frequency bandwidth is from 600 kHz to 1 MHz. The signal acquisition circuit uses Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) to obtain the flexible programmable ability and powerful data processing. Its resolution is 14 bit and maximum sampling frequency is 40 MHz. The acquisition algorithm uses digital phase sensitive detection to obtain the amplitude and phase information of NMR signal. Tests show that a range of common NMR experiments can be performed with our system. The CPMG echo train with high SNR is acquired successfully.

To supply the cathode voltage for the two gyrotrons (140 GHz/1 MW/3 s) of the electron cyclotron resonant heating system on HL-2A, a high-voltage power supply (HVPS) based on pulse step modulator (PSM) with rated output of 80 kV/200 A has been built. Because the storing energy of the PSM HVPS is much lower than traditional HVPS, it is beneficial to load protection. In the PSM HVPS, there are eight dry-type multiwinding transformers; each transformer has 14 secondary windings. The main insulation of the multiwinding transformer reaches to 150 kV. There are 112 switch power supplies in the PSM HVPS; the output voltage can be regulated from 0 to 80 kV by modulating their delay time and pulsewidths. To realize two gyrotrons parallel operating and respective quick protection for the loads, two solid-state high voltage modulators (SSHVM) based on insulated gate bipolar transistor are applied in the power supply. The over-current and over-voltage protection are executed by turning off the PSM HVPS and the SSHVM. The protection time is ${ . A fully digital controller based on digital signal processor and field programmable gate arrays has been developed to ensure the stability of the output voltage of the PSM HVPS. The design circuit and elements are described, and the test results of the PSM HVPS are given in this paper.

Real‐time control will play an important role in the operation and scientific exploitation of the new generation fusion devices. This paper summarizes the real‐time systems and diagnostics developed by the Portuguese Fusion Euratom Association based on digital signal processors and field programmable gate arrays.