Digitally Current Controlled DC-DC Switching Converters Using an Adjacent Cycle Sampling Strategy

The digital double loop current control become the promising technique for digital switching DC-DC converters. In this paper a novel current control technique, named cycle-borrow control is proposed and studied, which has faster loop transient response than the time delay control, and its requirement to loop processing speed can be relaxed as compared with the deadbeat current control. The cycle-borrow valley current control laws of buck DC-DC converters with four different pulse width modulations are derived, and their stabilities are analyzed. A simple digital slope compensation (DSC) method which doesn't need any extra slope compensation circuit is proposed to eliminate the sub-harmonic oscillations of cycle-borrow control. The simulation results show that, the transient response performance of dual-edge modulations is better than that of single-edge modulations. The cycle-borrow control technique is especially benefit to high-frequency digitally controlled switching DC-DC converters.

Digital average current (DAC) control of switching dc-dc converters with single-edge modulation (trailing-edge and leading-edge modulations) is studied in this paper. To calculate the average inductor current with minimum calculation time and appropriate precision, a new algorithm, called the four-point-mean (FPM) algorithm, is proposed. The DAC control laws with trailing-edge and leading-edge modulations are derived by using FPM algorithm, and their stabilities are studied. The subharmonic oscillation of DAC controlled switching dc-dc converters is investigated and analyzed. It is shown that both digital slope compensation and digital reposition compensation of the ac component of duty ratio for digitally controlled switching dc-dc converters cannot eliminate the subharmonic oscillation of DAC controlled switching dc-dc converters. Instead, a new method, called digital triangle compensation, for the elimination of the subharmonic oscillation of DAC controlled switching dc-dc converters is proposed and studied. Experimental results are given to verify the analysis results.

The sub-harmonic oscillation of digital average current (DAC) control buck converter with single-edge modulation (trailing-edge modulation and leading-edge modulation) is investigated in this paper. It has been shown that both digital slope compensation (DSC) and digital reposition compensation (DRC) of duty ratio ac component can not be used to eliminate the sub-harmonic oscillation of DAC control buck converter with single-edge modulation. To eliminate the sub-harmonic oscillation of DAC control buck converter with single-edge modulation, a new method, called as digital triangle compensation (DTC), is proposed and studied. Simulation results are given to verify the analysis results.

Since parabolic current control has fast transient response and high control precision with constant switching frequency, it is an attractive current control strategy for voltage source inverters. The employment of parabolic current control delivers great performance on current waveform control or voltage waveform control. The implementation of parabolic current control usually requires high speed digital-to-analog converters (DACs) to generate a pair of parabolic carriers as the control band. With increases in switching frequency, this requirement becomes more critical because the speed of DAC limits the update rates of the parabolic carriers. This impacts the smoothness and punctuality of the parabolic control band. To solve this issue, a parabolic current control based digital current control strategy is proposed in this paper. The proposed method uses the sensed current of the output inductor to calculate the next duty-cycle. To improve the transient response speed, a duty-cycle adjustment is presented. The performance of the proposed digital control method is verified in simulation.

This paper describes an improved current tracking control strategy about cascaded H-bridge static var generator (SVG). This control strategy can not only increase dynamic response speed and power quality but also enhance the reliability of the grid. The working principle of the reactive power compensation is analyzed, then mathematic model of the cascaded H-bridge SVG is established, the model is discrete to be a discrete mathematic model. The discrete-time static observer is constructed and an improved dead-beat current control strategy is proposed. By comparing the dead-beat control and the current feed-forward coupling control, this dead-beat control has multitarget advantage. And by testing on a 10-KV 2-Mvar reactive power compensation system, the advantage of the dead-beat current tracking control is tested. Simulation and experimental results show that this control strategy can improve the dynamic performance and sine degree of the waveforms.

In this paper, we propose three advanced digital predictive current-mode control (DPCC) algorithms based on a simplified estimation method of duty cycle lost time for asymmetric half-bridge (AHB) LED constant-current driver. They are the digital predictive peak current mode control(DPPCC) algorithm based on leading-edge modulation, the digital predictive quasi-valley current mode control(DPqVCC) algorithm based on trailing-edge modulation, and the digital predictive quasi-average current mode control(DPqACC) algorithm based on double-edge modulation. Simulation and experimental results demonstrate that the three DPCC algorithms can effectively offset the effect of delay on digital control performance, which confirms the superiority of DPqACC. When the DPqACC is applied, the series-load-jump transition times are below 4.5 ms, the maximum load adjustment rate is 0.5%/ V, and the output current can be tuned continuously between 0.3 A and 4.5 A with the longest transition time of 1 ms. Moreover, the three DPCC algorithms are capable of compensating for low-frequency ripples due to the rapid regulation speed of the inner loop. With the electrolytic capacitance removed without additional ripple compensation, the maximum peak-to-peak value of the low-frequency secondary ripple is 0.1163 A (2.91%) when the input is 400 53sin(2ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>lin</i></sub> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> ) V and the output is 4 A. This approach provides an excellent solution for the digital design of low-ripple AC-DC LED constant-current drivers without electrolytic capacitance.

A novel fully digital FPGA-based current controller for switched reluctance machines is presented in this paper. The digital current controller provides PWM and hysteresis band modulation in a seamless way and allows complex rotor position based shaping of the phase currents to optimize torque ripple and acoustic behavior. Arbitrary phase current waveforms can be stored in a position-addressed memory. The FPGA based implementation ensures flexible scaling and adaptation to various machine designs and inverter topologies. Experimental results prove the feasibility and performance of the chosen approach.

A digital peak voltage (DPV) predictive control for switching dc-dc converters is proposed and studied in this paper. With the predictive control technique, the duty ratio in each switching cycle is usually calculated and predicted based on the status in the previous switching cycles. Therefore, at least a one-switching-cycle time delay usually exists in predictivPe control, which significantly degrades the control performance of digital controlled switching dc-dc converters. To eliminate this time delay and to improve the control performance, an improved DPV (IDPV) predictive control technique is then proposed and studied. The control laws of DPV and IDPV with different pulsewidth modulations are derived, and their stabilities are analyzed. A simple digital slope compensation method is proposed to eliminate the subharmonic oscillation of DPV and IDPV control laws. The steady-state and transient performances of DPV and IDPV controlled buck converters are investigated by simulation and experiment. The comparison studies among DPV, IDPV, and digital peak current (DPC) control show that the transient performances of IDPV and DPV are much better than that of DPC and that IDPV is better than DPV.

From the cost-effective product point of view, it is very important to design a current controller with the highest utilization factor of current capacity of power devices. This can be accomplished by a current controller without overshoot irrespective of the varying bounds of control voltage in PWM power converters. This paper suggests a novel digital current controller which has a deadbeat current control response without steady state errors and deals with the design method of the controller for PWM power converters. The superior performance of the suggested controller is verified through extensive digital simulations performed by SIMULINK/MATLAB and is compared with those of a state deadbeat controller and a tracking anti-windup PI controller. Simulation results show that the suggested controller guarantees the full utilization of current capacity of power devices.

A new all-digital current control technique is presented in this paper. The current control is based on Ramptime current control technique, where multisampling is chosen as the sampling strategy due to its ability to provide higher accuracy. The resultant current control is called Digital Ramptime current control. The performance of the new current control is compared with the original Ramptime in an active power filter experiment. Results show that with sufficient sampling, the performance of Digital Ramptime is satisfactory.

Performance of conventional digital current controllers is constrained by transport delays within the feedback acquisition chain, as well as by delays inherent to the pulse width modulation. In this paper, we introduce a novel current controller which provides a very high closed-loop bandwidth, improves the robustness and disturbance rejection, and eliminates the noise and sampling errors in the feedback path. In order to achieve these goals, we suppress the transport delays by introducing an improved execution schedule of the control interrupt and by inserting a cascaded multiplier of differential character. With the novel gain setting rule, the closed-loop bandwidth reaches 17% of the sampling frequency, disturbance rejection capability is doubled, the step response has a negligible overshoot, and the robustness is characterized by the vector margin of 0.65. Experimental verification is performed using an experimental setup with a three-phase inverter, digital controller, and a permanent magnet synchronous motor.

Interactive digital control using PMBus protocol can significantly improve performance, efficiency and reliability in high frequency low voltage DC (LVDC) microgrid applications using online optimization through shared clock and data. Modeling and analysis of digitally controlled standalone DC-DC converters, considering finite sampling delays, have been well reported in the past; however, modeling and analysis of fast scale stability and performance limits, under finite sampling delay and clock shift, have not been investigated so far in digitally controlled LVDC microgrids. This paper considers an intermediate bus architecture (IBA), consisting of an intermediate bus converter (IBC) followed by a point-of-load (PoL) converter, under clock-synchronized digital current mode control (DCMC). Considering the IBA dynamics, a discrete-time (DT) framework is proposed, and DT small-signal models are derived for stability and performance analysis. It is shown that the clock shift between individual converters and the sampling delays of their corresponding digital controllers have significant impacts on the fast-scale stability of the overall IBA system, which may lead to severe fast-scale instability with complex nonlinear phenomena and resulting in much higher (inductor) current ripple and RMS quantities. Simulation case studies are presented, and the stability boundaries are found to be consistent with the analytical predictions. The proposed framework will be helpful to design stable digital control in DC microgrids.

For permanent magnet synchronous motors (PMSMs) supplied with a voltage source inverter, current control strategies are commonly implemented under the synchronously rotating reference frame. In order to simplify the system structure, three-phase currents can be measured with a single DC-link current sensor using the phase current reconstruction technique. However, it still needs to follow the conventional AC current control approach. In this paper, a DC-link current control method for PMSMs is proposed to further simplify the control system. The problem of phase current control was separated into the problems of amplitude control and phase control. Then, amplitude control was achieved using a closed-loop controller directly tracking the DC-link current; while phase control was achieved by AC-side pulse width modulation (PWM) following the phase angle of back electromotive force. The compensation for nonlinear distortion of the inverter was taken into account during the control process. Finally, the proposed method realized three-phase current control with a single current sensor and controller, and achieved the purpose of electromagnetic torque control. Experimental results demonstrate the effectiveness of the proposed method.

This paper represents the digital current mode control for a multi-module bidirectional converter intended for battery charging/discharging applications. The digital current mode control is adapted to achieve equal current sharing and good dynamic performance. The predictive control is used for the digital current compensation and the direct method is adapted to the digital voltage compensation. The control parameters for the digital compensations are designed and fine-tuned using the SISO tool in MATLAB software. Theoretical predictions are confirmed with both MATLAB simulations and measurements on an experimental prototype converter.

The boost type dc-dc converter is used for compensation of dc bus voltage in the dc power feeding system such as the renewable energy system. It should be operated stably to improve reliability of the system. The peak current mode control is applied to operate stably because the boost type dc-dc converter tends to be unstable. However, a peak value of reactor current cannot be captured in the digital controller. In this paper, a digital peak current mode control boost converter with conversion from current to frequency and using a frequency detector for a peak current detection in real time is presented. The effectiveness of the proposed method is verified by the comparison of the transient response under changing an input voltage between the conventional PID control and the proposed method.