Directory-based cache coherence scheme using number-balanced binary tree

Large-scale MIN-based shared-memory multiprocessor systems have long shared memory latency. Private caches can improve memory access latency but they may suf fer from the cache coherence problem and potentially lower data locality due to data sharing and multiproces sor scheduling. These two problems also increase shared memory load and may result in frequent memory stalls. In this paper, we evaluate the performance of memory caches, a cache memory placed in front of shared memory, in a large-scale multiprocessor system in the presence of pro cessor caches. The memory cache is shown to have good performance and scalability.

Cache Coherence in Multiprocessors: A Survey

Open Core Protocol (OCP) is a standard on-chip core interface specification. The current release is flexible and configurable to support the communication needs of a wide range of Intellectual Property cores, and is now in widespread use. However, it does not support system-level coherence. This paper summarizes an effort within the OCP-IP cache coherence working group on incorporating cache coherence extensions into OCP, which is expected to have strong impact on the MPSoC industry. In this paper, we propose a backward-compatible coherent Open Core Protocol interface and discuss the design challenges and implications introduced. This interface is flexible and can support a range of coherence protocols and schemes: we show how it can specify a snoopy bus-based scheme as well as a directory-based scheme. The correctness of the specification and models was verified using NuSMV, via exploring the entire state space for the two basic coherence schemes.

Computer systems are extensively being used in today’s era and the advancement in computer systems has led to the evolution of various technologies. As the efficiency of the computer systems is to be enhanced, the usage of cache memory becomes a must. The cache memory problems occur when multiprocessor systems are used. When multiple processors are processors share a common memory pool, the problem of cache coherence occurs. Cache coherence is a state in which the cache memories of the processors must stay in coherence with each other. The data should be updated in all the cache systems. Various protocols are used to ensure cache coherence. This study delineates the cache memory architecture, cache coherence, and the issues that arise due to non-consistent data in the cache of multiprocessor systems. Moreover, this study also delineates the protocols of the cache coherence and also describes in detail the MISE protocol. This study will provide an in-depth review of cache, cache coherence, and the issues associated with cache coherence along with the solution.

The major applications of multiprocessor system-on-a-chip (SoC) comprises of heterogeneous processors on a single chip. In this kind of integration, major problem is the cache coherence problem i.e. Maintenance of data integrity. In this paper, we propose a record based methodology to remove the cache coherence problem in heterogeneous multiprocessor platforms with shared and private memories. As shown in our simulation results, a performance improvement up to 18.75% is achieved while using proposed approach in four different benchmarks on LIMES simulator as compared to three other snoopy cache coherence protocols Dragon, Berkeley and MESI.

The problem of cache coherence in large-scale shared-memory multiprocessors has been addressed using directory-schemes. Two problems arise when the number of processors increases: the network latency increases and the implementation cost must be kept acceptable. The authors present a tree-based cache coherence protocol called the scalable tree protocol (STP). They show that it can be implemented at a reasonable implementation cost and that the write latency is logarithmic to the size of the sharing set. How to maintain an optimal tree structure and how to handle replacements efficiently are critical issues the authors address for this type of protocol. They compare the performance of the STP with that of the scalable coherent interface (SCI) (IEEE standard P1596) by considering a classical matrix-oriented algorithm targeted for large-scale parallel processing. They show that the STP manages to reduce the execution time considerably by reducing the write latency. >

High-performance multiprocessor systems built around out-of-order processors with aggressive branch predictors execute many memory references that turn out to be on a mispredicted branch path. Previous work that focused on uniprocessors showed that these wrong-path memory references may pollute the caches by bringing in data that are not needed on the correct execution path and by evicting useful data or instructions. Additionally, they may also increase the amount of cache and memory traffic. On the positive side, however, they may have a prefetching effect for memory references on the correct path. While computer architects have thoroughly studied the impact of wrong-path effects in uniprocessor systems, there is no previous work on its effects in multiprocessor systems. In this paper, we explore the effects of wrong-path memory references on the memory system behavior of shared-memory multiprocessor (SMP) systems for both broadcast and directory-based cache coherence. Our results show that these wrong-path memory references can increase the amount of cache-to-cache transfers by 32%, invalidations by 8% and 20% for broadcast and directory-based SMPs, respectively, and the number of writebacks by up to 67% for both systems. In addition to the extra coherence traffic, wrong-path memory references also increase the number of cache line state transitions by 21% and 32 % for broadcast and directory-based SMPs, respectively. In order to reduce the performance impact of these wrong-path memory references, we introduce two simple mechanisms - filtering wrong-path blocks that are not likely-to-be-used and wrong-path aware cache replacement - that yield speedups of up to 37%.

The core of current-generation high-performance multiprocessor systems is out-of-order execution processors with aggressive branch prediction. Despite their relatively high branch prediction accuracy, these processors still execute many memory instructions down mispredicted paths. Previous work that focused on uniprocessors showed that these wrong-path (WP) memory references may pollute the caches and increase the amount of cache and memory traffic. On the positive side, however, they may prefetch data into the caches for memory references on the correct-path. While computer architects have thoroughly studied the impact of WP effects in uniprocessor systems, there is no comparable work for multiprocessor systems. In this paper, we explore the effects of WP memory references on the memory system behavior of shared-memory multiprocessor (SMP) systems for both broadcast and directory-based cache coherence. Our results show that these WP memory references can increase the amount of cache-to-cache transfers by 32%, invalidations by 8% and 20% for broadcast and directory-based SMPs, respectively, and the number of writebacks by up to 67% for both systems. In addition to the extra coherence traffic, WP memory references also increase the number of cache line state transitions by 21% and 32% for broadcast and directory-based SMPs, respectively. In order to reduce the performance impact of these WP memory references, we introduce two simple mechanisms—filtering WP blocks that are not likely-to-be-used and WP aware cache replacement—that yield speedups of up to 37%.

The drastically reduced costs and improved performance of fiber optic components in recent years offers an opportunity to economically incorporate high-bandwidth optical communication links within a large-scale multiprocessor system. In this paper, the design, implementation, and initial performance of a fiber optic bus for a tightly coupled multiprocessor system are discussed. This optical bus ulitizes a multiple fiber-multiple star configuration with data rates of up to 80 MHz. It transmits bus control line information by repetitively scanning the control lines and transmitting their states as a packet of bits. It is currently being used for a 30-processor system called the Heidelberg Polyp, which has a custom bus design. However, the design approach is a general one that could easily be adapted to other buses, especially asynchronous buses such as the VME bus.

Aiming at the Cache coherence problem that brings by multiple processor cores of CMP(Chip multiprocessors) sharing the single memory space, this paper introduces a new kind of Cache coherence--CSC(Coherence with SC-Cache) based on write-through and write-back mechanism, which contains SC-Cache (Shared Coherence Cache) module. Experiments show that the protocol reduces the number of bus transactions, to a certain extent improves the efficiency of processor data access.

Appropriate solution of the well-known cache coherence problem in shared memory multiprocessors is one of the key issues in improving the performance and scalability of these systems. Hardware methods are convenient because of their transparency for software. They also offer good performance since they deal with the problem dynamically. Hardware cache coherence schemes can be principally divided into two large groups: directory and snoopy protocols. This survey underlines their principles and summarizes a relatively large number of relevant representatives from both groups. The coherence problem in multilevel caches is also briefly considered. Special attention is devoted to cache coherence maintenance in large scalable shared memory multiprocessors. >

As faults are unavoidable in large scale multiprocessor systems, it is important to be able to determine which units of the system are working and which are faulty. System-level diagnosis is a long-standing realistic approach to detect faults in multiprocessor systems. Diagnosis is based on the results of tests executed on the system units. In this work we evaluate the performance of evolutionary algorithms applied to the diagnosis problem. Experimental results are presented for both the traditional genetic algorithm (GA) and specialized versions of the GA. We then propose and evaluate specialized versions of Estimation of Distribution Algorithms (EDA) for system-level diagnosis: the compact GA and Population-Based Incremental Learning both with and without negative examples. The evaluation was performed using four metrics: the average number of generations needed to find the solution, the average fitness after up to 500 generations, the percentage of tests that got to the optimal solution and the average time until the solution was found. An analysis of experimental results shows that more sophisticated algorithms converge faster to the optimal solution.

Approximate performance/cost analysis of m-level hierarchical multiprocessor systems

Processor scheduling policies for multiprocessor systems can be broadly divided into space-sharing and time-sharing policies. Space-sharing policies divide the system processors into a number of partitions and each partition is exclusively allocated to a single job. In time-sharing policies, processors are temporally shared by jobs. Several space-sharing and time-sharing policies have been proposed for small-scale shared-memory systems and require a central run queue and/or central scheduler. The central queue scheduler poses serious scalability problems for large-scale multiprocessor systems. Furthermore, space-sharing and time-sharing policies have their advantages and disadvantages. In this paper, we propose a new multiprocessor scheduling policy that eliminates contention for the central queue/scheduler. Our hierarchical scheduling policy (HSP) is a self-scheduling policy and uses a hierarchical run queue organization to facilitate processor allocation to jobs. We show that the HSP policy is considerably better than purely space-sharing and purely time-sharing policies over a wide range of system and workload parameters of interest.

Recently multicore technology has enabled development of hundreds or thousands core processor on a single chip. However, on such multicore processor, cache coherence hardware will become very complex, hot and expensive. This paper proposes a parallelizing compiler directed software coherence scheme for shared memory multicore systems without hardware cache coherence control. The general idea of the proposed method is that an automatic parallelizing compiler parallelize coarse grain task, analyzes stale data and line sharing in the program, then solves those problems by simple program restructuring and data synchronization. The proposed method is a simple and efficient software cache coherent control scheme built on OSCAR automatic parallelizing compiler and evaluated on Renesas RP2 with 8 SH-4A cores processor. The cache coherence hardware on the RP2 processor is only available for up to 4 cores. The cache coherence hardware can also be turned off for non-coherence cache mode. Performance evaluation was performed using 10 benchmark programs from SPEC2000, SPEC2006, NAS Parallel Benchmark (NPB) and MediaBench II. The proposed method performed as good as or better than hardware cache coherence scheme while still provided correct result as the hardware coherent mechanism. For example, the proposed software cache coherent control (NCC) gave us 2.63 times speedup for SPEC 2000 equake with 4 cores against sequential execution while got only 2.52 times speedup for 4 cores MESI hardware coherent control. Also, the software coherence control gave us 4.37 speed up for 8 cores with no hardware coherent mechanism available.