Divisional Load-Modulated Balanced Amplifier With Extended Dynamic Power Range

In this work, a new particle swarm optimization (PSO) method with dynamic nonlinear self-adaptive hyperparameters (DNSHs) (PSO-DNSHs) is proposed for radio frequency (RF) power amplifier (PA) design. The theory and advantages of this method are described and analyzed. Based on the proposed PSO-DNSH method, a multioctave PA and a broadband pseudo-Doherty load-modulation balance amplifier (PD-LMBA) are designed. The multioctave single-ended PA achieves an output power exceeding 40.3 dBm, a drain efficiency greater than 60.9%, and a gain of over 10.3 dB between 0.5 and 3.6 GHz. While the broadband PD-LMBA shows a saturated output power of 41.1–43 dBm, a saturation drain efficiency of 57.7%–77.6%, a 6-dB output power back-off (OBO) DE of 47.3%–64.6%, and a 10-dB OBO DE of 51.2%–68.4%. Compared with other existing PSO-based methods, the results demonstrate that the proposed method not only achieves better performance for both PAs, but also shows faster convergence capability. Modulated signal tests along with the digital predistortion (DPD) are also conducted for both PAs, 20-MHz 5G new radio (NR) signal with 6- and 10-dB peak-to-average power ratios (PAPRs) are used for single-ended PA and PD-LMBA, respectively. Excellent linearity is achieved for both PAs.

Most existing behavioral models of the radio frequency (RF) power amplifiers assume that power amplifiers are memoryless devices. But in broadband communication systems, memory effects of the RF power amplifiers are significantly observed. The traditional memoryless models can no longer accurately depict the input-output relationship of power amplifiers. This paper investigates power amplifiers memory effects and a pre-distortion method is proposed for linearizing RF power amplifiers with memory effects. A valid behavioral model based on the Volterra series is suggested to treat memory effects. Since the characteristics of amplifiers change during transmission time, a recursive least squares algorithm with size- fixed observation matrices is developed to update the parameters of the proposed power amplifiers model. The identification algorithm can decrease computational complexity and data storage space and facilitate real-time online identification. Simultaneously, the pre-distortion model is constructed to simulate. Simulation results show that the proposed method can effectively compensate for the nonlinear distortion and memory effects of RF power amplifiers. The model's accuracy is used to evaluate power amplifiers memory effects by the enormalized mean square error (NMSE). In the end, simulation and evaluation of this pre-distortion system proceeded, and the power spectral density estimation was also applied to calculate the adjacent channel power ratio.

Design of high-efficiency power amplifier (PA) is one of the key challenges to realize green radios, wherein digital predistortion (DPD) is deployed to reduce the PA’s power back-off and thus increase its power efficiency. As the bandwidth of the transmit signal increases, stringent requirements are posed on the DPD linearization performance with limited sampling rate and dynamic range for the analog-to-digital converter (ADC) in the DPD feedback channel. In this paper, under a fixed ADC sampling rate, novel DPD architecture is proposed to compensate for the PA nonlinearity with limited ADC dynamic range. In the feedback channel of the proposed architecture, an extra radio frequency (RF) cancellation chain is introduced to eliminate the linear component of the PA amplified signal, and thus the requirement on the ADC dynamic range can be significantly reduced. Subsequently, by accurately estimating the loop delay and attenuation of the cancellation chain, the baseband replica of the RF cancelling signal is recovered, and the original PA output signal is rebuilt to estimate the DPD coefficients. Finally, experiments show that for the long term evolution (LTE)-advanced signals, the proposed architecture can achieve an adjacent channel leakage ratio lower than −47.6 dBc, which outperforms the conventional DPD by about 3.4 dB, with the effective bits of the ADC being reduced by 4.4 and a power added efficiency of 43.8% with 7.3 dB power back-off being observed for a fabricated Doherty PA with 50-dBm saturation power.

With the high interest in digital modulation techniques which are very sensitive to the PA nonlinearity, modern wireless communication systems require the usage of linearization techniques to improve the linear behavior of the RF power amplifier. The powerful and cheap digital processing technology makes the digital predistortion (DPD) a competitive candidate for the linearization of the PA. This thesis introduces the basic principle of DPD, its implementation on FPGA and the adaptive DPD system. The linearization of 4 PAs with DPD technique has been introduced: for the hybrid class AB PA operating at 2.6 GHz with a WiMAX testing signal, 33.7 dBm average power, 29.6 % drain efficiency, 13 dB ACPR and 9 dB NMSE improvement have been obtained; for the hybrid Doherty PA operating at 3.4 GHz with an I/Q testing signal, 35.0 dBm average power, 36.8 % drain efficiency, 12 dB ACPR and 13 dB NMSE improvement have been obtained; for the MMIC class AB PA operating at 7 GHz with an I/Q testing signal, 29.4 dBm average power, 25.7 % drain efficiency, 12 dB ACPR and 12 dB NMSE improvement have been obtained; for the two-stage PA operating at 24 GHz with an I/Q testing signal, 23.5 dBm average power, more than 14.0 % drain efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The DPD algorithm has been implemented on FPGA with two methods based on LUT and a direct structure with only adders and multipliers. The block RAM on the FPGA board is chosen as the table in the LUT methods. The linearization performance for these three methods is similar. The test PA is the hybrid Doherty PA mentioned above and the test signal is the I/Q signal with 7.4 dB PAPR. 35.1 dBm average power, 36.8 % efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The cost of logic resources for the direct structure method is the largest with 1,172 flip-flops, while the number of flip-flops for the two LUT methods are 263 and 583, respectively. A new adaptive algorithm has been proposed in this thesis for the adaptive DPD system. This new algorithm improves the performance in extracting the model parameters in complex number domain. With the experimental data from a combined class AB PA, the final accuracy of the model extracted by the new algorithm has been improved from -20 dB to about -40 dB and the converge speed is faster

In this work, a Doherty power amplifier is presented for IMT-Advanced system at 450–470MHz frequency band. An imperfect Quarter-wave transmission line, which consisted of two shunt capacitors and a series microstrip line, is adopted to replace the bulky impedance inverter quarter-wave transmission line for designing the Doherty power amplifier (PA). Both the traditional and proposed structures for the Doherty power amplifiers were implemented. Comparing with the traditional Doherty amplifier, the size of the circuit and the manufacturing costs are decreased obviously. The measurement results of the proposed Doherty PA exhibit good performance as well as the traditional Doherty power amplifier. For a input signal with a 7.8dB Peak to Average Power Ratio (PAPR), the measured drain efficiency of the proposed Doherty power amplifier is 48.5% at an average output power of 43.0 dBm, which is a 7.8dB backed — off the peak output power. Moreover, in order to improve the linearity of the proposed Doherty power amplifier, the augmented Hammerstein and polynomial predistorter are used to linearize the proposed Doherty power amplifier. After digital predistortion, the adjacent channel leakage ratio (ACLR) reaches −45.5dBc at an average output power of 43.0 dBm, which can satisfy the requirements of the IMT-Advanced systems.

The nonlinearity of power amplifiers is one of the principal reasons degrading the transmission quality in the wireless communication systems comprising the single-carrier frequency-division multiple access (SC-FDMA) utilised for the up-link in the LTE system. In this letter, we analysed and predicted the nonlinearity of SC-FDMA signals in spectrum respect. Owing to the nonlinearity of radio frequency (RF) power amplifiers, an analytic model is established on the basis of a third-order intercept point (), which is fit for weakly nonlinear systems and devices. The research results confirm that the spectrum regrowth with RF power amplifier is specified and measured efficiently. This sort of design inherits the advantages of orthogonal frequency division multiplexing (OFDM) and is of great help for both designing RF power amplifiers and further improving the spectrum regrowth with pre-distortion outside channels, extended to other wireless systems based on SC-FDMA modulation.

Two differential radio frequency (RF) power amplifier (PA) architectures are presented in this paper both of which can be used to implement a wideband Doherty PA. Classic PA architecture is compared to a SB (SB) PA in order to determine an architecture that offers the widest input impedance match without external component tuning. Both amplifiers presented in this paper have been designed to output an average of 10.5 dBm of continuous wave (CW) power with 1.8 V supply. The classic PA architecture is tuned to 1.9 GHz central frequency by external components and has a bandwidth of 500 MHz at S11=−10 dB. The SB PA architecture has an operating range spanning from 0.8 GHz to 2.2 GHz at S11=−10 dB. SB PA has a higher power added efficiency (PAE) at output compression point (OR-P1dB) in the whole 1.2 GHz–2.4 GHz range by 3 %–7 % with a peak efficiency of 31 %. The presented results indicate that a SB RF PA architecture can be implemented designing a wideband Doherty PA.

In this paper, a novel frequency component controllable digital predistortion (DPD) for radio frequency (RF) power amplifiers (PAs) is proposed. The detailed analysis and experimental results demonstrate that the target band or frequency component to be linearized can be arbitrarily chosen according to user's demand by employing the proposed approach, which makes digital predistortion much more flexible in future wireless communication systems.

This paper presents the Direct Current (DC) power budget analysis and Radio Frequency (RF) frontend system design considerations of a medium Power Amplifier (PA) with average power output of 1watt. The PA system analysis is performed in a simulation environment for three linearization usage scenarios such as, Back-off, Digital Pre-Distortion (DPD) and Analog Pre-Distortion (APD) schemes. In the Back-off mode, the total RF frontend power consumption is 35.87 watt and with the usage of DPD topology the power consumption is 32.76 watt while with APD topology, the power consumption is 23.74 watt. The APD topology considers a Commercial off the Shelf (COTS) design topology with using moderately non-linear PA device operation. As compared to the back-off operation, the DPD scheme has got a 8.6% estimated relative power saving and the APD provides an estimated relative power saving of 33.8%.

In this paper, a novel modified Doherty power amplifier (DPA) that allows for extended output back-off (OBO) range, improved power utilization factor (PUF), and increased peak power over a broad bandwidth is proposed. It starts with an in-depth analysis of the modified DPA circuitry that first revealed the ability to control the impedances seen by the main transistor versus frequency by properly setting the magnitude and phase of the ratio between the peaks of the combining currents. This is then exploited to maximize the peak power and enhance the achievable bandwidth. Furthermore, a complex-to-real output matching network is incorporated in the auxiliary path and its parameters are carefully chosen to produce proper load modulation while satisfying the required peak combining current ratio. For validation purpose, a DPA prototype is designed to operate over the frequency range of 1.35-2.05 GHz with an OBO of 9 dB. Under the continuous-wave excitation, the DPA prototype maintained the drain efficiency (DE) of 52%-55% and 65%-75% at 9-dB OBO and peak power, respectively, over the entire targeted band. In addition, the measured peak power and PUF were about 42 dBm and higher than 0.9, respectively. The linearizability of the DPA prototype using digital predistortion (DPD) with memory was assessed while being driven with a 40-MHz carrier-aggregated signal with a peak-to-average power ratio of 8.9 dB and at an average output power of 33 dBm. When the carrier frequency is swept over the entire band, the measurement revealed an adjacent channel leakage ratio of better than -46.5 dBc after DPD with an average DE of 49.3%-53%.

In this article, we present a novel decomposed vector rotation (DVR)-based recurrent neural network behavioral model for digital predistortion (DPD) of radio frequency (RF) power amplifiers (PAs) in wideband scenarios. By representing memory terms of DVR with recurrent states and redesigning the piecewise modeling, we propose a novel recurrent DVR scheme. To ensure stable operation and enhanced modeling accuracy, we integrate the recurrent DVR into the gated learning mechanism of the modified Just Another NETwork (JANET). Experimental results confirm that the proposed DVR-JANET model provides much improved linearization performance with significantly reduced model complexity compared with the recent existing models.

Utilizing asymmetric Doherty technology, this paper designs a high-efficiency radio frequency (RF) power amplifier (PA) for 5G base station applications. To improve the performance of PA and narrow the gap between simulations and practices, we use compatibility methods to design the circuit, which keeps the layout dynamically adjustable. By incorporating redundant U-shaped microstrip lines, the impedance matching network can be dynamically fine-tuned during debugging based on real-time hardware conditions. Furthermore, independent debugging paths for both main and auxiliary amplifiers are designed to enable the multi-stage debugging strategy. Performing separate debugging for each branch first, followed by combined debugging ensures both amplifiers achieve optimal operation states. The proposed strategy improves debugging efficiency while achieving precise parameter optimization. To verify the feasibility of the scheme proposed in this paper, we use CGHV40030F transistors to design a Doherty PA worked at 3.5 GHz and complete the hardware implementation and tests. Simulations and practice results prove that the architecture of asymmetric Doherty increases the back-off efficiency, and the compatibility design can make debugging easy and align the practice results closely with the simulations. We observe the saturation drain efficiency of 73.5% and the back-off efficiency of 47.5% from measurements, which confirms the effectiveness of the proposed compatibility design approach.

In massive multiple-input–multiple-output (MIMO) systems, circuit differences among power amplifiers (PAs) lead to poor nonlinear behavior consistency. This makes it difficult to linearize multiple PAs with shared digital predistortion (DPD). Pre-tuning circuit differences and improving circuit performance with low-power, low-cost analog devices is a desirable method. This article proposes a technology for the co-optimization of nonlinear behavior consistency and efficiency/linearity of PAs. This technology uses the passive adjustable mismatch network to fine-tune the load impedance of PAs. Two strategies are proposed for configuring network parameters. Their contribution is to achieve co-optimization, as well as fast selection of network parameters. In the theoretical part, a numerical model is presented to demonstrate the mechanism of tuning circuit differences. Based on simulation and test, the relationship between nonlinear behavior consistency, efficiency, and linearity, as well as the impact of circuit differences on them, is pointed out. At the same time, an efficient co-optimization method is proposed. The feasibility of this method is verified by numerical simulation and test of nine Doherty PAs from the same batch. In the test, when the shared DPD signal excites multiple PAs, the maximum improvement in adjacent channel power ratio (ACPR) is 7.73 dB; when the original signal excites multiple PAs, the maximum improvement in efficiency and normalized mean square error (NMSE) is 7.25% and 4.12 dB, respectively. In addition, this technology shows excellent adaptability in the dynamic carrier frequency range of 2340–2480 MHz.

In this article, a fully integrated dual-band gallium nitride (GaN) Doherty power amplifier (DPA) based on multi-resonant circuits (MRCs) is presented. A lumped T-type network in combination with the output capacitances of the main and auxiliary transistors is able to realize the quarter-wavelength transformer (QWT) in DPA, and its component values are totally decided by the operating frequency, given a certain characteristic impedance. MRCs are proposed to exhibit the required component values at two different frequencies. By replacing each component in the T-type network with an MRC, a dual-band QWT can be achieved. An integrated dual-band DPA is implemented in a commercial 0.25- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaN-HEMT process to validate the proposed method. The fabricated DPA shows a saturated output power of 43.8–44.7/44.4–44.8 dBm, a 6-dB back-off drain efficiency (DE) of 41%–46%/41.5%–47%, and a saturated DE of 49%–52%/56%–59% in 3.35–3.6/4.8–5.2 GHz, with a compact size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.8\times3.5$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Applying a 100-MHz OFDM signal with a 7.8-dB peak-to-average power ratio (PAPR), an average efficiency of 37%/40% and an average power of 37/37 dBm are measured at 3.5/5.0 GHz, and the adjacent channel power ratio (ACPR) is better than −49 dBc after digital predistortion (DPD). To the best of our knowledge, the proposed DPA is the first demonstration of fully integrated dual-band GaN DPAs.

A new load modulation combiner (LMC) having the capability of back-off control is proposed for a Doherty power amplifier (DPA). The proposed LMC consists of two transmission lines tied at the combining node, and a shunt element across the other ends of the transmission lines. The shunt element of the LMC becomes virtually open-circuited at the peak power level and allows the carrier amplifier to have an arbitrary load impedance at the low power level. The operating principle and circuit structure of the DPA based on the proposed LMC are presented in detail. The proposed DPA was implemented using GaN-HEMT for the 3.5 - 4.0 GHz band. Using a 5G NR signal with a peak-to-average power ratio (PAPR) of 7.9 dB and signal bandwidth of 100 MHz, the implemented DPA showed drain efficiency (DE) of 49.6 - 54.4% and power gain of 11.1 - 13.0 dB at an average output power of 34.5 dBm. An adjacent channel leakage power ratio (ACLR) was obtained as −50.4 - −45.0 dBc at the average power level with a digital pre-distortion (DPD) technique.