Doherty Power Amplifier with Dynamic Power Dividing Network for Enhanced Efficiency

Fifth generation communication networks promise extremely high data throughputs, low latencies, and ultra-high reliability by employing small cells in high density networks. This will increase the use of highly inefficient microwave power amplifiers, that exhibit efficiencies sometimes as low as 10% for advanced multi-carrier waveforms. To overcome these inefficiencies and enable next generation technology development, the internal distributed behaviour of the packaged microwave power transistor has to be fully characterised, which is impossible using conventional port-based measurements. In this dissertation, the development of a set of multiphysics measurement techniques that capture the distributed electrical, electromagnetic, and thermal device behaviour is described. These new multiphysics measurement techniques enable the characterisation and direct visualisation of the inefficient device performance, providing a basis for future design optimisation. The techniques combine a non-linear vector network analyser, electro-optic, load-pull and thermoreflectance measurement systems that enable large signal time-domain electrical, distributed multi-harmonic vector electric field (E-field), and transient and steady-state thermal measurements. The multiphysics measurement set-up was used to characterise various transistors and PAs including 260 W silicon (Si) laterally diffused metal oxide semiconductor (LDMOS) field effect transistors in both air-cavity ceramic and plastic packages, 25 W gallium nitride (GaN) on silicon carbide high electron mobility transistors (HEMTs), 250 W GaN HEMT and 360 W Si LDMOS Doherty power amplifiers. The E-field measurements enabled the first ever imaging of parametric odd-mode oscillations within multi-die packaged high-power microwave transistors. Additionally, the measurement system was used to verify the effectiveness of in-package oscillation suppression circuits. As high-resolution E-field measurements can be slow, a surrogate modelling-based measurement algorithm was implemented to accelerate measurements 10-fold. Transient thermal measurements helped to identify abnormal transistor finger-to-finger heating in GaN HEMTs and revealed thermal differences along the gate width in GaN-based asymmetric transistors for Doherty power amplifier applications.

Doherty power amplifier (DPA) with high efficiency at the output power back off is highly demanded for modern wireless communication systems to achieve high data rates and reduce the power consumption and operation costs. This paper presents a new design strategy for enhancing DPA’s back-off efficiency. New design strategy called asymmetrical matching network is used to achieve asymmetric operation, which helps to compensate for the low power delivered by the peaking stage in the conventional DPA. The simulation results showed an enhancement in the back-off efficiency, where the proposed design is able toachieve 46-52% drain efficiency at 8 dB output power back-off while maintains high efficiency of 73-80 % at saturation over the designed bandwidth of 3.4-3.6 GHz. The proposed design is suitable for high efficiency sub-6 GHz fifth-generation wireless applications.<br /><div> </div>

In this article, a novel high‐efficient Doherty power amplifier (DPA) is designed for linearity improvement from 2.1 to 2.4 GHz. The proposed DPA employs a pair of anti‐coupled lines loaded with a stepped impedance resonator to replace the λ/4 transmission line in the conventional DPA for harmonic suppression, phase compensation, and impedance transformation. The DPA is simulated, fabricated, and measured. As the measured results show, in the 2.1‐2.4 GHz band, the saturated output power is between 43.2 and 44.5 dBm with the saturated gain level between 10.2 and 11.5 dB. The saturated drain efficiency (DE) is between 60% and 70% with DE at 6 dB output power back‐off between 38% and 50%. Compared with the conventional DPA, the third‐order intermodulation distortion is reduced by 20 dB. The efficiency and gain have also been improved. The proposed DPA is feasible and applicable in modern wireless communication systems.

In this paper, we present a monolithic microwave-integrated circuit (MMIC) asymmetric Doherty power amplifier (ADPA) using 0.25[Formula: see text][Formula: see text]m gallium-nitride (GaN) process with a compact chip size of 2.9 mm × 1.9 mm in wireless transmitters. Two different power amplifiers are adopted to solve the contradiction between the output power and efficiency of the conventional Doherty power amplifier (CDPA). In addition, phase compensation and low Q impedance inverting network (IIN) technology are used in the input and output matching networks, respectively, to expand the bandwidth of the entire ADPA. The post-layout simulation results show that the designed ADPA has a saturation output power 42.5 dBm with 800 MHz bandwidth from 6.6 to 7.4 GHz. The ADPA demonstrates 36.8–41.8% power-added efficiency (PAE), whereas 44–54% drain efficiency (DE) is achieved at saturation power.

ABSTRACTIn this article, we present a simplified Doherty power amplifier (DPA) architecture for the easy implementation of dual‐band operation. The proposed DPA structure eliminates the 35 Ω quarter wavelength impedance inverters used in the conventional DPAs by matching the output impedances of the carrier and peak amplifiers of the DPA to other values (e.g., 100 Ω). The electrical lengths of the offset line and the phase compensation line are carefully chosen to enhance the Doherty effect (high efficiency at back‐off power level) at two assigned frequency bands. Broadband matching networks are also designed to increase the operation bandwidths at the two designed bands. To prove the design concept, a dual‐band DPA is designed and measured. In the first frequency band (550–650 MHz), the designed DPA provides 60.6–76.3% drain efficiency (DE) at full output power, 46–54.9% DE at 6 dB of output power back‐off (OBO); in the second frequency band (950–1050 MHz), the designed DPA provides 51.4–61.2% DE at full output power, 35–38% DE at 6 dB of OBO. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:953–956, 2015

This paper presents the dc and high-frequency performances of laterally diffused metal–oxide–semiconductor (LDMOS) transistors with superjunction (SJ) structures. The SJ-LDMOS transistors were fabricated using a 0.5-µm CMOS process. By utilizing a modified SJ/RESURF layout (Type I) or a tapered SJ layout (Type II) in our devices, better high-frequency performances and higher breakdown voltages are achieved compared with conventional SJ counterpart, owing to the suppression of the substrate-assisted depletion effect and the reduction of the drain resistance. For Type I device with an optimal SJ layout dimension, the cutoff frequency and the breakdown voltage are 3.7 GHz and 68 V, respectively. For Type II device with a smallest p-pillar width near the drain, they can be enhanced further and reach to 4.9 GHz and 83 V. These experimental results suggest that the SJ-LDMOS can be used in the RF power amplifiers.

This letter reports a high-efficiency gallium nitride (GaN) high-electron mobility transistor (HEMT) Doherty power amplifier (DPA) based on the class-E topology for wideband code-division multiple-access (WCDMA) applications. The class-E topology is employed as the carrier and peaking cells of the Doherty configuration. For validations, the proposed DPA is designed and implemented with 25-W GaN HEMTs at 2.14 GHz. For the proposed DPA, the power-added efficiency (PAE) and drain efficiency of 56.1% and 61.2% are achieved at 40 dBm (6-dB backoff power from Psat) for a continuous wave. For a 1-carrier WCDMA signal, the PAE of 44.8% is obtained with an adjacent channel leakage ratio (ACLR) of -31 dBc at 37 dBm, which is an 8.9% improvement over the conventional DPA with an ACLR of -36.4 dBc.

High-voltage (HV) metal-oxide-semiconductor field-effect transistors (MOSFETs) of the laterally diffused metal-oxide-semiconductor (LDMOS) type enable applications over a wide range of bias voltages by optimizing the combined structure of MOSFET and drift region at its drain side. We report a physically accurate compact resistor model of the LDMOS drift region, adapted to the special requirements of the combined structure with a MOSFET. In particular, the reported resistor model captures the effects of the 2-D current flow in the drift region with its complicated bias dependence. The resistor model considers two device-structure-dependent potentials, namely, the internal node potential within the highly resistive drift region and the potential underneath the gate overlap region. The consistent potential-based description over the complete LDMOS device is the key modeling technology for enabling the accurate reproduction of the bias-dependent 2-D current flow and the resulting <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics for a wide range of structure variations with a small number of only six fitting parameters. The reported quasi-2-D resistor model is implemented in the second-generation Hiroshima-university STARC IGFET Model-High Voltage (HiSIM-HV) compact models for HV MOSFETs and is expected to be useful for both, optimization of LDMOS circuits and devices.

This letter presents an approach to maximize the output power and efficiency of a Doherty power amplifier (PA). The conventional carrier PA having match, used in a symmetric Doherty PA, does not deliver the saturated high efficiency at the 6 dB back-off power but at the 5.5 dB back-off power due to the knee voltage effect. To solve the problem, the gate biases of the carrier and peaking PAs are adapted. The gate bias voltage of the carrier PA is optimized for a higher peak output power, delivering a 3 dB larger peak power at match. That of the peaking PA is also optimized to have the same peak power of the carrier PA. A Doherty PA with the concept is designed using a 45 W gallium nitride (GaN) high electron mobility transistors (HEMT) for the carrier and peaking cells at 1.94 GHz. The measured average output power, drain/power-added efficiencies and gain are 44.35 dBm, 60.5/57.2%, and 12.75 dB for a 10 MHz long term evolution (LTE) signal with a 6.5 dB peak-to-average power ratio (PAPR).

Nowadays energy efficiency (EE) of wireless communication systems has become a hot issue, yet the nonlinear effect and inefficiency of power amplifier (PA) have posed practical challenges for system designs to achieve high EE. However, most of previous work only considered linear PA. In this paper, we studies EE optimization concerning with I-way Doherty PA which has widespread use with I = 1 and I = 2 in orthogonal frequency division multiplex (OFDM)-based cognitive radio (CR) systems. The aim is to maximize EE with nonlinear PA subject to the total power budget, the interference constraint and the minimum rate requirement. Other than traditional methods, the problem is hard to solve directly due to the nonlinearity of PA, and a bisection search method tailored for nonlinear PA is adopted to achieve the sub-optimal solution. Numerical results demonstrate that if the PA's nonlinearity is not considered, the EE performance of OFDM-based CR systems can be severely overestimated by 34% at P max out = 80 W for 1-way Doherty PA. Meanwhile, the EE performance can be enhanced by approximate 32% if 2-way Doherty PA is utilized instead of 1-way Doherty PA.

A physical capacitance model is presented for the drift region in a laterally diffused metal-oxide semiconductor (LDMOS). It is derived as a surface-potential-based model of nodal charge for the drift region. The model is combined with BSIM4, which is for the intrinsic MOSFET region of LDMOS, and it is validated with TCAD and measurement data. The model accurately predicts the capacitance of each node for the entire bias region.

This work presents a wideband extended efficiency range symmetric Doherty power amplifier (DPA) operating from 3.3 to 3.6 GHz. The presented DPA uses parallel combining to increase the bandwidth over a conventional DPA, and phase exploitation to extend the high efficiency back-off point beyond 6dB. A detailed performance analysis with respect to frequency is presented for the phase exploited symmetric DPA with parallel load combining (PE-PDPA). To validate the presented technique, a prototype is designed using GaN HEMT devices, and simulation results demonstrate that the PE-PDPA achieves 60%-77% efficiency at saturation and 43%-54% efficiency at 8 dB back-off over the 3.3-3.6GHz operating band. The PA maintains 10 dB gain and an average of 43 dBm saturated power over the entire frequency range.

We propose a new efficiency enhancement technique of Doherty power amplifiers (DPAs) using virtual short stub. In this technique, the peaking amplifier branch was utilized as an inductive short stub at output power combing point at low power level. Using this technique, it is possible to transform the low-power load impedance seen from the carrier amplifier into higher impedance than that of classical DPAs. This leads to efficiency enhancement at larger power back-off than conventional DPAs (>6dB). The relation of efficiency enhanced level and the circuit topology for DPAs with the virtual short stub are analytically derived. The proposed technique was experimentally verified by fabricating a 3.5 GHz 40 Watt Doherty power amplifier using GaN HEMTs. An average drain efficiency of 51% and adjacent power leakage ratio of −50 dBc was obtained using 10MHz LTE test signals with 8.5dB peak-to-average power ratio.

In this work, a Doherty power amplifier is presented for IMT-Advanced system at 450–470MHz frequency band. An imperfect Quarter-wave transmission line, which consisted of two shunt capacitors and a series microstrip line, is adopted to replace the bulky impedance inverter quarter-wave transmission line for designing the Doherty power amplifier (PA). Both the traditional and proposed structures for the Doherty power amplifiers were implemented. Comparing with the traditional Doherty amplifier, the size of the circuit and the manufacturing costs are decreased obviously. The measurement results of the proposed Doherty PA exhibit good performance as well as the traditional Doherty power amplifier. For a input signal with a 7.8dB Peak to Average Power Ratio (PAPR), the measured drain efficiency of the proposed Doherty power amplifier is 48.5% at an average output power of 43.0 dBm, which is a 7.8dB backed — off the peak output power. Moreover, in order to improve the linearity of the proposed Doherty power amplifier, the augmented Hammerstein and polynomial predistorter are used to linearize the proposed Doherty power amplifier. After digital predistortion, the adjacent channel leakage ratio (ACLR) reaches −45.5dBc at an average output power of 43.0 dBm, which can satisfy the requirements of the IMT-Advanced systems.

This paper presents a high-efficiency broadband Doherty Power Amplifier (DPA) architecture for the S-band covering from 3.3GHz up to 3.55GHz, aiming on 5G applications. The DPA based on low-pass like output matching structure and modified higher back-off combining network was designed and fabricated. Continuous Wave (CW) measurement results show that the proposed PA delivers a saturated output power of more than 47.5dBm, and holds a Power-Added-Efficiency(PAE) of more than 600% (at 7.5dB back-off) at all frequencies except 3.3GHz, which is about 53% with a saturated PAE range of 47%-58% within bandwidth. Also the 20 MHz LTE modulation signal measurement achieves the high efficiency and linearity performance of DPA, with a PAE of more than 50.6% at 8.5 dB back-off and an ACPR of -46.7 dBc.