DoublePlay

We herein propose three novel optimization methods to accelerate distributed transaction processing into a geographically distributed database. The first optimization involves the parallelization of the write-ahead logging protocol. It allows multiple worker threads to synchronize log entries to the storage device simultaneously without any dependencies. The second optimization involves the grouped transfer of log entries from the leader to followers. This reduces the number of transmissions and effectively uses the network bandwidth. The third optimization involves the separation of the worker thread logic. By breaking the logic into the prepare phase and the commit phase, the worker threads at the leader node run asynchronously in parallel without waiting for responses from the follower nodes. The experimental results demonstrated that the proposed method achieved more than 10 million tps and less than 100 ms with client interactions through the network. The CPU utilization was almost 100%, which implied a dramatic reduction in synchronization in worker threads.

Researchers using High Content Screening systems generate thousands of fluorescently labeled cell images from which they measure subtle but important phenotypic changes summarized by dozens of parameters. Large image datasets and fast turnaround requirement have made the efficient High Content Analysis a challenging task. This paper studies multi-core based high performance image analysis and its application to data and compute-intensive High Content Analyses. A vertical parallelization strategy is employed and an automated parallelization framework is implemented to automatically dispatch image processing tasks. The strategy is based on allocation of different images to separate processors so that each image is analyzed sequentially on a single processor and multiple images are processed by separate processors in parallel. Experiments demonstrate that this approach, of a generic character, considerably increases throughput.

This paper describes a multibody dynamics algorithm formulated for parallel implementation on multiprocessor computing platforms using the divide-and-conquer approach. The system of interest is a general topology of rigid and elastic articulated bodies with or without loops. The algorithm divides the multibody system into a number of smaller sets of bodies in chain or tree structures, called “branches” at convenient joints called “connection points”, and uses an Order-N (O (N)) approach to formulate the dynamics of each branch in terms of the unknown spatial connection forces. The equations of motion for the branches, leaving the connection forces as unknowns, are implemented in separate processors in parallel for computational efficiency, and the equations for all the unknown connection forces are synthesized and solved in one or several processors. The performances of two implementations of this divide-and-conquer algorithm in multiple processors are compared with an existing method implemented on a single processor.

Summary form only given. The authors describe facilities which have been included in a configuration language called PCL to support the process of system installation. PCL is used to support the installation of two classes of distributed system. These are distributed applications where a single, 'logical' system is structured as a set of processes which may execute concurrently on separate processors and multi-copy applications where the same system is installed on several different nodes in a network. PCL can describe both hardware and software systems. This has allowed the authors to extend the language with a description of constraints on system installation and with facilities for specifying where particular software is to be installed. They use a special purpose installation tool (PCL-Install) to interpret installation instructions. The advantages of this approach are that installation procedures are easy to write and understand, the installation framework for a family of related systems can be defined and the model provides support for installation across heterogeneous networks. >

Hypothesis-oriented Multiple Hypothesis Tracking (HOMHT) recursively generates hypotheses on the origins of measurements and manages them, therefore it is computationally intensive. To speed up HOMHT for tracking hundreds of targets in real time, we propose a parallel implementation of this algorithm which distributes hypotheses into independent worker threads residing in multiple CPU cores. The implementation in this paper is based on object-oriented programming: each hypothesis object manages its target data all by itself and the generation and pruning of a hypothesis is achieved by its copy constructor and destructor functions. We evaluate this method by tracking 150 targets through 3 heterogeneous sensors in real-time with 32-best hypotheses running in 1, 2, 4, 8, 16 and 32 worker threads respectively. The results validate the method's scalability in which measurement fusion latency is approximately inversely proportional to worker thread count. We also make a pressure test by tracking 500 targets through 3 sensors, and HOMHT is able to run concurrently in real-time with 32 worker threads.

As the bytecode produced by the Java compiler is unoptimized, the bytecode generated from certain types of idiomatic Java code is inefficient for execution in an interpreter. This effect is amplified in a co-processor system, in which a single processor must process heap accesses and virtual method calls from multiple threads. Two types of optimizations are presented which can be performed directly on bytecode during class loading and which do not require a large amount of processing time. These optimizations are shown to improve performance greatly, up to 29 % in the Embedded Caffeinemark Benchmark suite. Even higher improvements were measured in multithreaded programs.

The paper investigates the evaluating task of the traffic as the registered number of vehicles of one of the three classes (a bus, passenger car or truck) that passed in a certain direction per unit of time, according to data from CCTV cameras in real time. For simplification this problem solving was divided into three components. They are registration of traffic flow objects and their classification, finding trajectories of fixed objects and determining traffic lanes, as well as counting objects in each direction. A comparative analysis of the existing algorithms, software and hardware systems that solve problems similar to the problems was carried out; also, a proprietary approach was proposed. The analysis describes the feasibility for developing their own approach due to the lack of an algorithm that meets all the requirements, such as estimating the traffic on the basis of data from surveillance cameras. Besides, the existing hardware and software systems are of the high cost and complexity. The YOLO artificial neural network was used to recognize objects on the frame in the form of rectangles containing the image of a vehicle. To build tracks, objects are compared frame-by-frame based on a set of characteristics, including a simple (average) perceptual hash and the coordinates of the corresponding rectangle. The developed algorithm for constructing trajectories of moving traffic objects, highlighting lanes of automobile traffic and counting vehicles is proposed as a software module. The testing results concerning the quality of the algorithm are introduced. The main advantages and disadvantages of the proposed approach are highlighted.

Future multicore processors will be more susceptible to a variety of hardware failures. In particular, intermittent faults, caused in part by manufacturing, thermal, and voltage variations, can cause bursts of frequent faults that last from several cycles to several seconds or more. Due to practical limitations of circuit techniques, cost-effective reliability will likely require the ability to temporarily suspend execution on a core during periods of intermittent faults.

Digital image correlation (DIC) method is a rapid development of photomechanics technology. The basic principle of the method is calculated the correlation between before and after deformation of the specimen surface speckle images, which is used to determine displacement and deformation. DIC measurement system includes hardware and software system. The former is the speckle image acquisition system, the latter are speckle image analysis algorithm and implementation procedures. Because the software analysis algorithm can achieve sub-pixel accuracy or even more, most of scholars have focused on the speckle image analysis algorithms. The system performance caused by the composition of hardware system has been less introduced. The hardware system mainly included the camera, lenses, lighting and other components. If hardware system is not perfect and stable, it will bring hundreds or even thousands of micro strain measurement error. These unfavorable factors make 2D-DIC inaccurate in small deformation tests. To some extent, it limits the application of 2D-DIC in the engineering practice. This paper analyzed that the various components of DIC hardware system impacted on the system performance, It was given that how to reasonably select the various components in the typical cases, as well as involved that the selection of 2D-DIC measurement system is applied to the actual engineering measurements in high temperature environment. These can provide support that 2D-DIC measurement system is better applied to the engineering practice.

After a deep analysis on how to use an image processing system to detect the missing holes on the motor carling, we design the whole system combined with the actual production conditions of the motor carling. Afterwards we explain the whole system's hardware and software in detail. We introduce the general functions for the system's hardware and software. Analyzed these general functions, we discuss the modules of the system's hardware and software and the theory to design these modules in detail. The measurement to confirm the area to image processing, edge detection, randomized Hough transform to circle detecting is explained in detail. Finally, the system result tested in the laboratory and in the factory is given out.

Any integrated circuit from simplest to complex it is possible to present faulty operation which can happen from various factors.Some circuits present faults which were imported during the manufacturing process, while failures can also presented during their operation.In order to determine if an integrated circuit has been manufactured correctly, or that it continues its functionality according to the specifications, it should successfully complete a process called testing.Few years ago, the need of high reliability in electronic circuits was limited in military and banking applications, where a dysfunction can have devastating results.However the electronic circuits present wide spread in a lot of sectors of our life, while at the same time the size of manufacture technology shrinks fast, the manufacturing testing receives important role in guarantee the quality and the reliability of final products.In this PhD thesis are proposed methodologies for self-testing problem of System-on-Chip, SoC and especially for communication controllers of these integrated circuits, as well as for symmetric multiprocessors with different interconnection schemes such as shared bus and crossbar switch.In the first chapters of this thesis we proposed a systematic methodology for self-testing of communication peripheral controllers that are integrated in a SoC.The proposed methodology is based in deterministic testing and is general and completely applicable in any communication peripheral.Moreover, we proposed a hybrid self-test methodology for SoC that combines the deterministic methodology with a semi-automated, pseudorandom methodology.In the second part of this thesis we presente a methodology for test routines scheduling of symmetric multiprocessors with different interconnection schemes such as shared bus and crossbar switch.The solution that we proposed has exceptional importance now that chip multiprocessors, or with multiple cores (multicores), or with multiple threads (multithread) are used more widely than never.The test scheduling methodology uses the parallelism of multiprocessors architecture in order to decrease dramatically the total test application time of the self-test programs.

An integrated hardware and software system is used in studying neural correlates of learning. The hardware system is designed to maximize experimental flexibility, while the software system is designed to maximize computer speed for data acquisition and programmer efficiency for data analysis.

Multiprocessor application performance can be limited by the operating system when the application uses the operating system frequently and the operating system services use data structures shared and modified by multiple processing cores. If the application does not need the sharing, then the operating system will become an unnecessary bottleneck to the application's performance.This paper argues that applications should control sharing: the kernel should arrange each data structure so that only a single processor need update it, unless directed otherwise by the application. Guided by this design principle, this paper proposes three operating system abstractions (address ranges, kernel cores, and shares) that allow applications to control inter-core sharing and to take advantage of the likely abundance of cores by dedicating cores to specific operating system functions.Measurements of microbenchmarks on the Corey prototype operating system, which embodies the new abstractions, show how control over sharing can improve performance. Application benchmarks, using MapReduce and a Web server, show that the improvements can be significant for overall performance: MapReduce on Corey performs 25% faster than on Linux when using 16 cores. Hardware event counters confirm that these improvements are due to avoiding operations that are expensive on multicore machines.

Autonomous underwater vehicles (AUVs) have many, scientific, military, and commercial applications because of their potential capabilities and significant cost-performance improvements. Typical AUV development requires critical system design and many costly at-sea trials during which systems specifications can be validated. Modeling and simulation provides a cost-effective method for carrying out preliminary component or system (hardware and software) testing and verification. Due to the complexity of most AUV development and their tight schedules, the simulated systems often differ considerably from the actual embedded architecture, thereby reducing the fidelity of the entire simulation. We adopted a hardware-in-the-loop (HIL) simulation approach that includes some level of the system's hardware and software. As expected, an HIL simulation requires all components be run under hard real-time constraint. The paper presents our implementation and considerations on HIL simulation for single and multiple vehicles. A brief mention of sensor and environment modeling is also provided.

The authors present an experimental study on a system which implements a pattern recognition algorithm (W.C. Lin, K.S. Fu, 1965, 1966) with a set of artificial neuron elements emulated on a multi-microprocessor hardware system. The algorithm is believed to be good for parallel processing utilizing the concept of information content, or entropy. The system used for the implementation study consists of four commercially available iSBC 286/12 single board microcomputers. They are configured to operate in parallel within the environment of the real-time operating system iRMX286. Thus, it is a multi-microprocessor and multitasking real-time processing hardware system. It is shown that the system with four microprocessors is 3.8 times faster than a single processor in operation speed with a recognition rate of 95%. Since the algorithm is a regionalism process in the feature space, the number of regions, and thus the number of microprocessors operating in parallel, can be increased to satisfy specific real-time requirements. >