Dry Etch Self-Aligned AlInAs/InGaAs Heterojunction Bipolar Transistors

A dry etch fabrication technology for high-speed AlInAs/InGaAs heterojunction bipolar transistors (HBTs) utilizing low-damage electron cyclotron resonance (ECR) CH4/H2/Ar plasma etching is detailed. Small-area (2×4 to 3×9 μm2 ) devices demonstrated current gains up to 160, unity gain cutoff frequency ( fT) of 57 GHz and a maximum oscillation frequency ( fmax) of 35 GHz. The dry etch process uses triple self-alignment of the emitter and base metals and the base mesa, minimizing the base-collector capacitance (CBC). These results represent the first report of a truly scalable process for In-based HBTs and demonstrate the ability of ECR plasma etching to provide smooth, degradation-free etching of III–V semiconductors.

Even with the copious advances in logic device fabrication, integration of new channel materials would represent a significant advance in CMOS technology. [1] Successful integration of new channel materials (III-V’s, Ge and SiGe) pose significant challenges for etch technology. Dry (plasma) etch technology can be used to pattern channel materials after they are deposited using an epitaxial process [2]; alternatively channels maybe inserted into bounded (for example an oxide) recesses (for example silicon) fabricated using etch technologies already developed for FinFET and SAQP applications. Less appealing is the use of wet processes that have troublesome crystallographic orientation dependencies. Dry etch technology for most new channel material candidates is not new. [3] Still, with dry etch technology there is the ever-present worry of damage. [4-6] High precision etch technology commonly referred to as atomic later etching (ALE) is an emerging viable option for new channel material integration. [7-10] Some approaches employ non-mainstream techniques such as neutral beam technology [8] or complex precursors. [10] Recent developments reinforce that conventional plasma etch technologies developed using concurrent engineering methods can meet the requirements for 7 and 5 nm logic fabrication. [7,11] This presentation will show how advanced plasma etch technologies provide a path for logic manufacture beyond 7 nm with a realistic picture of the trade-offs that must be handled for the introduction of III-Vs, Ge or SiGe. All in all, etch technologies if successfully implemented for new channel material integration relies of leveraging surface chemistry mechanisms. The presentation will be rounded out with a discussion of how first-principles methods (e.g., DFT methods) can be used to gain insight into important plasma –surface interaction mechanisms. S. Takagi et al., Japanese Journal of Applied Physics 54, 06FA01 (2015) Chen et al,. Nanoscale Research Letters, 7, 431 (2012) Plasma Etching of III–V Nitrides,” by R. Shul, in Processing of Wide Band Gap Semiconductors: Growth, Processing and Applications, 250 (2000), ed., S.J. Pearton F.D. Auret et al., Physica B, 407, 1497 (2012) Kasumandari et al., Appl. Phys. Lett., 103, 033511 (2013) “Dry Etching of Semiconductors at the Nano-and Micro-Scale” by S.J. Pearton in Vistas in Nanofabrication, (2012) A. Ranjan et al., J. Vac. Sci. Technol. A 34, 031304 (2016) S.D. Park et al., Appl. Phys. Lett. 91, 013110 (2007); C. T. Carver et al., ECS J. Sol. St. Sci. Tech., 4 N5005-N5009 (2015) S. M. George, Chem. Rev., 110, 111 (2010) S.D. Sherpa et al., J. Vac. Sci. Technol. A 35, 01A102 (2017)

The incorporation of dry etch processes for mercury cadmium telluride (HgCdTe) infrared device fabrication is becoming critical for the infrared community as we advance toward the production of high-density devices. Dry etch processes are cleaner than wet etch processes. In addition, dry etches are highly anisotropic and are capable of producing the small features required by the more advanced device architectures. However, the incorporation of dry etch processes into device fabrication often affects the surface quality, producing roughened surfaces and variations in composition. Consequently, the identification of suitable dry etch processes to produce high quality infrared devices is essential. In this investigation, three different plasma etching tools (reactive ion etching, electron cyclotron resonance, and remote microwave) were used to etch HgCdTe with hydrogen. The hydrogen interaction with HgCdTe at similar etch depths was examined with spectroscopic ellipsometry and atomic force microscopy. Variations in surface roughness and composition obtained when etching with the three plasma etching tools are reported and the significance of energetic ions on surface quality is discussed.

In order to be useful for high speed digital circuit applications, double-barrier SINIS or SIS'IS junctions must be nonhysteretic, possess high critical current densities (j/sub c/>1 kA/cm/sup 2/) and high characteristic voltages V/sub c//spl sim/0.3 mV, where V/sub c/=I/sub c/R/sub sub/ and R/sub sub/ is a characteristic (subgap) resistance damping the junction in the operating range of voltages. This requires high transparencies of barriers and small interlayer thicknesses. Data are presented on fabrication and Josephson properties of SIS'IS junctions with j/sub c/ up to 10 kA/cm/sup 2/ at 4.2 K. It is shown that the asymmetry of double-barrier structure starts playing a major role at high j/sub c/ (i.e., at thin, high transparency barriers) as evidenced by the temperature dependences of the critical current, the value of the current deficit in the I-V characteristics, and the appearance of multiple Andreev reflection peaks in differential conductance of the junctions.

Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance

This thesis describes the development of a dry plasma etch smoothing technique to replace the conventional Chemical Mechanical Polishing process within a device manufacturing scheme in the semiconductor industry. An important semiconductor manufacturing process is 3D wafer packaging, which allows vertical stacking of wafer die. 3D wafer packing represents a significant component of the total wafer level processing cost. A critical step in the 3D packaging process flow is the Chemical Mechanical Polishing process. Replacement of the CMP process step with a corresponding dry etch can yield significant time and cost savings. This is achievable through reductions in metrology and wafer handling requirements and lower volumes of materials needed for plasma-etch based processes compared with CMP. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200 nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6 nm is demonstrated, which is comparable to a virgin silicon wafer. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where these surface scratches are falsely identified as defects. The quality of the plasma polished surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification process followed by a roughness reduction iteratively, to produce a smooth surface without visible grind marks. Further work describes the application of the smoothing process to microneedles, with the aim of improving the process flow. Smoothing of silicon carbide has been performed. Finally, an extension of the TSV reveal process is described, called extreme thinning, with the development of a predictive model to minimize final total thickness variation. Silicon smoothing can also be beneficial to this application.

DC, RF and noise characteristics of advanced InP/InGaAs and Si/SiGe heterojunction bipolar transistors (HBTs) were measured and modeled in a broad frequency range. Equations for systematically modeled correlated noise in bipolar transistors and their implementation in the compact models HICUM/L0 and L2 are proposed. The models are verified for advanced SiGe HBTs up to 300 GHz by hydrodynamic device simulation and by results from the Boltzmann transport equation. The verified model was used for analyzing the noise of advanced InP/InGaAs and Si/SiGe HBTs. Compared to Si/SiGe HBTs a higher noise at lower frequencies was observed in InP/InGaAs HBTs due to a higher base recombination current. InP HBTs shows a good noise performance beyond 100 GHz and due to their better $$f_{\mathrm{T}}\,\times ~BV_{\mathrm{CE0}}$$fT×BVCE0 product can compete with advanced Si/SiGe HBTs for LNA design at mm-wave frequencies.

A fast and inexpensive scheme for etch rate prediction using flexible continuum models and Bayesian statistics is demonstrated. Bulk etch rates of MgO are predicted using a steady-state model with volume-averaged plasma parameters and classical Langmuir surface kinetics. Plasma particle and surface kinetics are modeled within a global plasma framework using single component Metropolis Hastings methods and limited data. The accuracy of these predictions is evaluated with synthetic and experimental etch rate data for magnesium oxide in an ICP-RIE system. This approach is compared and superior to factorial models generated from JMP, a software package frequently employed for recipe creation and optimization.

The wet etching process in photomask fabrication could not meet requirements for small features for high density devices having optical proximity correction (OPC) features. Therefore, a dry etching process should be employed in mask making. However, there are some critical issues in dry etching process: one of the most important issues is critical dimension (CD) variation across the mask due to the loading effect during dry etching. CD errors caused by dry etch process are known to be originated from non-uniformity of plasma, non-vertical resist profile, and loading effect due to the various pattern densities. In case of loading effect, we are concerned about only macro-loading effect rather than micro-loading effect because the aspect ratio in the photomask is very small compared to that in the wafer. After dry etch, the patterns surrounded with large chrome area have large CDs because of the lower etch rate. We found that the macro-loading effect was about 5-10nm. And the effective range of the loading effect is amount to more than 10mm. In order to improve the CD variation caused from loading effect, we should optimize process conditions based on plasma uniformity, etch selectivity, resist profile, etc. However, it is a time consuming job. In this paper, we present a new method to improve loading effect, which is used for correcting e-beam proximity effect. Once we know the degree of loading effect, we can compensate it by allocating various doses at necessary locations.

Process optimizations have been done to produce 'Fine Pattern' reticles whose minimum target sizes are under 720 nm. 'Zero Bias' process for binary Cr reticles can be achieved with our dry etching process using ZEP-7000 blanks. MEBES-4500 exposure on resist films of 300 nm and dry etching with Magnetic Enhanced Reactive Ion Etching (MERIE) system are adopted. It is shown that adjusted develop condition weakens thinning effect of resist in sub-micron area due to proximity effect of exposure, and MERIE system with Gas Assist Etching (GAE) also improves pattern resolution. CD shift due to 'Loading Effect' is small and resist patterns are perfectly printed as Cr pattern with negligible deterioration of CD linearity. Much improved CD distribution in the area of 132 mm square can be obtained. In production of MoSiON-based attenuated-PSM (Att- PSM), CD shifts between Cr and MoSiON except OPC patterns (such as serif and scattering-bar) can be estimated about 30 nm. It is also shown that there are few defects after dry etching, and 'Zero Defect' reticles are obtained in most cases. Through the all results, validity and probability of our process to produce 'Fine Pattern Reticles' near the half- micron are discussed.

Not only are amorphous oxide semiconductor thin film transistors (TFTs) extremely sensitive to the processing of the active layer, but subsequent layer processing can also impact the performance. Due to this sensitivity, many surface treatments and passivation techniques for the active layer have been developed, but the influence of the etching of the active layer itself has not been explored extensively. These etch steps are especially critical in the manufacture of flexible microelectronics, for which process conditions are inherently limited by thermal stability of the plastic (<200 °C) and incompatibility of the plastic substrate with highly oxidizing chemical environments. Here, a novel dry etch process is compared to typical wet etch process in the context of flexible zinc indium oxide TFT array fabrication on plastic. The dry etch process provides superior control of the sidewall profile and the etch selectivity. These improvements using a dry etch approach decrease the off current of the TFT by 3 orders of magnitude from 2.65 nA for the wet etch process to 0.71 pA using the dry etch with a concurrent improvement in the device yield to 100% (for 120 transistors) with the dry etch. Additionally, the subthreshold slope improves from 1.9 to 1.0 V/decade, while the saturation mobility (6.5 cm2/V s) is not impacted by the etch process.

Background: CR-39 nuclear track detectors are widely used in various fields, including science, technology, astronomy, and environmental preservation, to detect and register heavy ions, neutrons, and alpha particles. Objective: This study aims to determine the optimal etching duration for CR-39 nuclear track detectors by comparing etching methods: The wet etching (using a water bath) and the dry etching technique (using dielectric barrier discharge (DBD) plasma). Methods: The traditional etching method involved immersing CR-39 detectors in a sodium hydroxide (NaOH) solution at 70 °C for varying durations. The dry etching method employed employs a non-thermal DBD plasma system to etch solid-state nuclear track detectors (SSNTDs) without the use of chemical solutions. Results: Photomicrographs revealed that tracks from chemical etching became clearly visible after 1 hour and developed at 5 hours. In contrast, the dry etching technique was significantly faster; tracks began to appear after just 1 minute of DBD plasma etching and were fully developed at 5 minutes. The optimum track density for DBD plasma was 20340±56 tracks/mm2 at 3 minutes, whereas the traditional water bath method achieved an optimum track density of 5238.0±5.7 tracks/mm2 at 2 hours. The shorter etching duration in the dry method likely facilitates the emergence of latent tracks without overlap. Conclusions: The bulk etch rate (VB) for CR-39 detectors using the dry DBD plasma etching technique was faster compared to the traditional chemical etching method. This demonstrates the efficacy of the dry etching process in significantly reducing etching time required for etching SSNDs.

Effects of H 2 plasma exposure on [formula omitted] heterojunction bipolar transistors

An accurate compact circuit simulation model has been developed for the large-signal, high-frequency behavior of GaAs single heterojunction bipolar transistors (HBTs). A unified, physically-based, quasistatic collector charge function models both base-collector capacitance and collector transit time. It naturally handles collector space-charge effects, full-depletion of the collector n region, and the dependence of the high-field electron velocity in GaAs on electric field and temperature. An improved charge expression accounts for the Kirk effect. This formulation has produced excellent model fits to measurements of AlGaAs-GaAs HBTs.

Summary form only given, as follows. Active Matrix Liquid Crystal Display (AMLCD) market is projected to quadruple in size by the next millennium. Within the last year, the flat panel display (FPD) marketplace has been very dynamic and the product requirements are evolving rapidly towards larger size, higher resolution, lower power consumption and at ever lower price targets. These market forces are driving FPD process technology innovations at a breathtaking pace. For FPD processing, dry etching is in an analogous position to that in IC processing back in the early 80s when the industry was posed to make the transition from wet to dry etch. Up to now, dry etching has only seen widespread manufacturing applications in Si and SiN processing. Within the last year, both Applied Komatsu Technology (AKT) and Lam Research (LRC) have introduced next generation FPD dry etch cluster tools. These tools offer improved process characteristics and enhanced capability that present many new opportunities to apply dry etching to FPD processing. In the next couple of years, dry etching will be a key enabler for architectural innovation. In the paper, these new dry etch processes and their applications in FPD display are reviewed.