Dual pillar spin-transfer torque MRAMs for low power applications

Spin transfer torque magnetic random access memory (STT-MRAM) is an emerging memory technology which exhibits nonvolatility, high density, high endurance, and nano-second read and write times. These characteristics make STT-MRAM suitable for last-level cache and other embedded applications. The STT-MRAM bit-cell consists of a magnetic tunnel junction (MTJ) which is composed of two ferromagnetic layers (free and fixed layers) and one insulating layer in between. As STT-MRAM arrays become denser to meet cost and requirements of high performance computing, the distance between adjacent MTJ bits reduces. This aggravates the magnetic coupling from free and fixed layer of one MTJ bit to its neighbors. Even though magnetic coupling is expected to become stronger as MTJ scales down, its impacts on static and dynamic properties on MTJ is relatively unexplored. In this paper, we present a model of the magnetic field coupling in high-density MTJ arrays for three different types of MTJ stacks and evaluate the effect of magnetic field induced coupling on static and dynamic properties. Lastly, we show how process induced variations in MTJ characteristics affect the magnitude of magnetic coupling and their effect on the electrical characteristics of the STT-RAM arrays.

High thermal stability, a fast switching time, and a low switching current are key characteristics of merit for realizing gigabit-class magnetic random access memory (MRAM). Especially, the switching current needs to be reduced significantly for creating high-density MRAM. In order to realize these necessary features, a number of magnetic tunnel junction (MTJ) structures have been proposed. A previous study of ours led to the proposal of a novel Curie-temperature-controlled hybrid thermo-magnetic structure for MRAM, for the purpose of improving these advantageous properties. This paper presents an analysis of the switching time and switching current by using micromagnetic simulation techniques for comparing our structures with various MTJ structures that have been proposed recently. We confirm that our novel structure can improve the switching characteristics of MRAM. The results of our analysis revealed that a 44% lower switching current and a 32% faster switching time can be achieved compared with the conventional structure.

Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate for next generation memory as it is non-volatile, fast, and has unlimited endurance. Another important aspect of STT-MRAM is that its core component, the nanoscale magnetic tunneling junction (MTJ), is thought to be radiation hard, making it attractive for space and nuclear technology applications. However, studies on the effects of ionizing radiation on the STT-MRAM writing process are lacking for MTJs with perpendicular magnetic anisotropy (pMTJs) required for scalable applications. Particularly, the question of the impact of extreme total ionizing dose on perpendicular magnetic anisotropy, which plays a crucial role on thermal stability and critical writing current, remains open. Here we report measurements of the impact of high doses of gamma and neutron radiation on nanoscale pMTJs used in STT-MRAM. We characterize the tunneling magnetoresistance, the magnetic field switching, and the current-induced switching before and after irradiation. Our results demonstrate that all these key properties of nanoscale MTJs relevant to STT-MRAM applications are robust against ionizing radiation. Additionally, we perform experiments on thermally driven stochastic switching in the gamma ray environment. These results indicate that nanoscale MTJs are promising building blocks for radiation-hard non-von Neumann computing.

A new class of spin-transfer torque magnetic random access memory (STT-MRAM) is discussed, in which writing is achieved using thermally initiated magnonic current pulses as an alternative to conventional electric current pulses. The magnonic pulses are used to destabilize the magnetic free layer from its initial direction, and are followed immediately by a bipolar electric current exerting conventional spin-transfer torque on the free layer. The combination of thermal and electric currents greatly reduces switching errors, and simultaneously reduces the electric switching current density by more than an order of magnitude as compared to conventional STT-MRAM. The energy efficiency of several possible electro-thermal circuit designs have been analyzed numerically. As compared to STT-MRAM with perpendicular magnetic anisotropy, magnonic STT-MRAM reduces the overall switching energy by almost 80%. Furthermore, the lower electric current density allows the use of thicker tunnel barriers, which should result in higher tunneling magneto-resistance and improved tunnel barrier reliability. The combination of lower power, improved reliability, higher integration density, and larger read margin make magnonic STT-MRAM a promising choice for future non-volatile storage.

Electron-spin based data storage for on-chip memories has the potential for ultrahigh density, low power consumption, very high endurance, and reasonably low read/write latency. In this article, we analyze the energy-performance characteristics of a state-of-the-art spin-transfer-torque based magnetic random access memories (STT-MRAM) bit-cell in the presence of parametric process variations. In order to realize ultra low power under process variations, we propose device, bit-cell and architecture level design techniques. Such design methods at various levels of design abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications.

Probabilistic nature of magnetic tunnel junctions (MTJs) poses a new type reliability challenges for spin-transfer-torque MRAM (STT-MRAM). Switching current and thermal barrier need to be co-optimized to control bit error rate margins of STT-MRAM. This requires deeper understanding about thermal disturbance and soft write errors of MTJ devices. In this tutorial, we review basic mechanisms that govern the bit error rates of STT-MRAM and discuss the effect of the probabilistic nature of MTJ devices on STT-MRAM reliability engineering.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is an emerging memory technology, which is seen as a promising replacement for CMOS based on-chip memories. It has several distinctive advantages such as nonvolatility, high endurance, high density, CMOS compatibility and scalability among others. However, retention failure has emerged as a major reliability concern for this technology due to the large variations in retention time because of process variations and temperature effects. The conventional solution to mitigate retention failures is to use scrubbing at regular intervals to prevent accumulation of errors, based on the worst case retention time of the memory array. But this leads to large performance and energy overheads. In this work, we propose a process variation and temperature aware scrubbing technique, where we cluster the cache lines into different groups based on their retention times and use different scrubbing intervals for each of these groups. In addition, the scrubbing interval is adjusted at run-time based on the operating temperature, to guarantee target error rate requirements. Our results show that for a 512KB cache, a group size of 4 can reduce the performance and dynamic energy overheads of scrubbing by 97%, under the same error rate constraint.

One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. In this paper, we estimate the STT-MRAM cell reliability under fabrication- and aging-induced process variability, by evaluating its failure probability. We analyze the effect of control voltage tuning on the fresh and aged cell failure probabilities and, as a result, we propose a power- and aging-aware circuit level variability mitigation technique based on control voltage tuning. We observed that increasing the values of control voltages, the cell failure probability is reduced at different extends (according to the control voltage under variation), but also that the power consumption is increased. As a result, we have identified the control voltage with the highest impact on the fresh cell reliability, and on the endurance of the cell under study. Subsequently, by performing a power/reliability trade-off analysis, the appropriate value of this control voltage is determined.

Magnetic tunnel junctions with perpendicular anisotropy form the basis of the spin-transfer torque magnetic random-access memory (STT-MRAM), which is non-volatile, fast, dense, and has quasi-infinite write endurance and low power consumption. Based on density functional theory (DFT) calculations, we propose an alternative design of magnetic tunnel junctions comprising Fe(n)Co(m)Fe(n)/MgO storage layers with greatly enhanced perpendicular magnetic anisotropy (PMA) up to several mJ/m2, leveraging the interfacial perpendicular anisotropy of Fe/MgO along with a stress-induced bulk PMA discovered within bcc Co. This giant enhancement dominates the demagnetizing energy when increasing the film thickness. The tunneling magnetoresistance (TMR) estimated from the Julliere model is comparable with that of the pure Fe/MgO case. We discuss the advantages and pitfalls of a real-life fabrication of the structure and propose the Fe(3ML)Co(4ML)Fe(3ML) as a storage layer for MgO-based STT-MRAM cells. The large PMA in strained bcc Co is explained in the framework of Bruno's model by the MgO-imposed strain and consequent changes in the energies of dyz and dz2 minority-spin bands.

The effects of fluorine inclusion in the aluminum oxide tunnel barrier on the electrical characteristics and the interface structure of magnetic tunnel junctions were studied. Compared with conventional junctions without fluorine, the fluorine-containing junctions exhibit larger and nearly constant tunneling magnetoresistance (TMR) values over a wide range of oxidation times and exhibit a smaller bias dependence for TMR. X-ray photoelectron spectroscopy indicates that the fluorine forms an aluminum oxyfluoride barrier together with an oxygen and that the fluorine-rich oxyfluoride layer at the barrier top surface plays an important role in the formation of the highly insulating barrier, resulting in nearly ideal barrier/electrode interfaces without a detrimental magnetically dead layer.

In the era of big data, massive data requires processing efficiently. However, the limited data bandwidth between the memory and the processor in conventional computer systems could not meet the requirement of data transferring. Computing in-memory has been considered an effective solution to address this problem. In this paper, based on the spin transfer torque-magnetic random access memory (STT-MRAM), a computing in-memory architecture with as few peripheral circuits as possible is proposed. This computing in-memory architecture gives the specific reference cell so that two rows in one array can be activated simultaneously to perform bitwise logic operations, such as OR/NOR and AND/NAND. In addition, with technology scaling down, STT-MRAM suffers from high sensitivity to process variation, which results in more device mismatch in a sense circuit. Additionally, the negative bias temperature instability (NBTI) seriously affects the life of PMOS transistors used in a sense circuit. In this paper, a high-reliability sense amplifier for computing in-memory with STT-MRAM is proposed. By using two self-enabled switching transistors, the proposed sense amplifier not only can decrease the NBTI effect on PMOS transistors but also can achieve a low sensing error rate. Using a CMOS 40[Formula: see text]nm design-kit and an accurate compact model of the STT magnetic tunnel junction (MTJ), mixed transient and statistical simulations have been present to demonstrate the functionality and performance of the proposed circuits.

CoFeB/MgO/CoFeB magnetic tunnel junctions (MTJs) have revolutionized modern spintronics, driving extensive efforts to optimize their properties such as spin polarization, perpendicular magnetic anisotropy, and switching speed. Here, a novel MTJ architecture is demonstrated, integrating ferrimagnetic CoTb to the conventional CoFeB/MgO/CoFeB MTJ structure, achieving both superior device performance and unique functionalities. The key innovation lies in the realization of sign‐tunable tunneling magnetoresistance (TMR), where the TMR ratio undergoes a dramatic transition from +33% (300 K) to ‐58% (30 K). This sign reversal, occurring at the ferrimagnetic compensation temperature (TM = 212 K), stems from strong ferromagnetic (CoFeB‐Co sublattice) and antiferromagnetic (CoFeB‐Tb sublattice) couplings in the hybrid CoFeB/CoTb layers. Around TM, a distinctive spin‐flop mediated TMR sub‐loop is further observed at high field which provides additional resistance states. These resistance states can not only be switched by external magnetic field but also by thermal operations. Furthermore, energy‐efficient field‐free switching is demonstrated through synergistic spin‐orbit torque (SOT) and spin‐transfer torque (STT) effects, achieving all‐electrical switching of MTJ at JSOT = 5 MA cm−2 with a minimal 4.1% STT current incorporation. This innovative ferrimagnetic MTJ architecture establishes a new platform for developing next‐generation spintronic devices with superior functionality, operational versatility, and performance metrics.

We analyze the augmentation of spin-transfer torque (STT) MRAM with electrically driven selective phase transition of a threshold switch (TS) to enhance the read operation. This paper provides a comprehensive discussion on necessary design considerations for TS augmented (TSA) MRAMs. We deduce constraints for read and write biasing that yields improved read operation of TSA MRAMs. We explain the dependence of read/write performance metrics on read/write biases and the properties (resistance and critical currents for transitions) of the TS. With proper device-circuit optimization, TSA MRAM shows up to 70% larger sense margin, ~27% higher data stability with ~40% less power for read operation compared to STT MRAM (in nominal condition). We evaluate the impact of variation on TSA MRAM through Monte Carlo simulations. We report that even with variation induced spread in the distribution of bit-line voltages, TSA MRAM provides $\sim 1.7\times $ larger voltage differential between parallel and antiparallel states. For the write operation, the TSA MRAM consumes ~10% less average power and demands only ~5% more write time extension than the STT MRAM to achieve the same level of variation tolerance.

Perpendicular spin-transfer-torque magnetic random access memory (p-STT-MRAM) is a promising candidate memory device for replacing dynamic random access memory (DRAM) facing with 10-nm sub scaling down. In addition to scaling down, p-STT MRAM has many advantages like fast write/read speed (~10ns) as DRAM, low power consumption (<1pJ), high endurance (>1014), and non-volatility (retention time > 10 years). But to replace DRAM, there are several challenges to be solved. First, high tunneling magneto-resistance (TMR) ratio for read sensing margin. Second, low critical current density(J C) for low power consumption. Third, thermal stability(Δ) for long retention time to save data. And also these parameters should be achieved at 350oC annealing temperature of the back-end-of line (BEOL) to be commercialized. Among them, thermal stability is closely related with cell size. As a cell size of MTJ decreases to achieve a high density memory device, thermal stability decreases with retention time, thus it is not easy to implement both high density and non-volatile memory device simultaneously by decreasing the cell size of MTJ. In our study to solve this issue, we propose the p-STT multi-level cell (MLC) magnetic tunnel junction (MTJ) because MLC MTJ can satisfy both high density and non-volatile memory device at the same time. In particular, we design the MTJ structure with dual free layers and MgO tunnel barriers, so that the MTJ can demonstrate four resistance states. In addition, we investigated the effect of the thickness of two free layers and MgO tunnel barriers on two magneto-resistance (MR) and switching voltage. In our experiments, the p-STT MTJ spin-valves were fabricated on 12-inch-diameter Si/ SiO2/W/TiN wafers by utilizing a 12-in. multi-chamber-cluster magnetron-sputtering system under a high vacuum (less than 110-8 Torr) without breaking the vacuum. Then, all samples were subject to ex-situ annealing at 350℃ at a back end of line (BEOL) for 30 minutes under a magnetic field of 3 tesla. In our presentation, we present how to optimize the thicknesses of two free layers and MgO tunnel barriers. In addition, we repot how the magnetic behavior and the resistance of MTJ is affected by magnetic and how the magneto-resistance of MTJ is closely related to the crystallinity of two MgO tunnel barriers. Acknowledgements This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2017R1A2A1A05001285)

Spin Transfer Torque (STT) switching realized using a Magnetic Tunnel Junction (MTJ) device has shown great potential for low power and non-volatile storage. A prime application of MTJs is in building non-volatile Look Up Tables (LUT) used in reconfigurable logic. Such LUTs use a hybrid integration of CMOS transistors and MTJ devices. This paper discusses the reliability of STT based LUTs under transistor and MTJ variations in nano-scale. The sources of process variations include both the CMOS device related variations and the MTJ variations. A key part of the STT based LUTs is the sense amplifier needed for reading out the MTJ state. We compare the voltage and current based sensing schemes in terms of the power, performance, and reliability metrics. Based on our simulation results in a 16nm CMOS, for the same total device area, the voltage mode sensing scheme offers 75% lower failure rates under threshold voltage (Vth) variations, 4.9X higher tolerance to MTJ resistance variations, 19% less delay, and 64% lower active power compared to the current sensing scheme.