Dynamic branch prediction using neural networks

Dynamic branch prediction in the high-performance processors was a specific instance of a general time series prediction problem that occurred in many areas of science. In contrast, most branch prediction research focused on dynamic two-level branch prediction techniques, a very specific solution to the branch prediction problem. In this paper, we introduced a kind architecture of loop detector and b-cache pipeline restorer which were based on GAs dynamic two-level branch prediction. The processors which brought the extend architecture can reduce redundancy decode of program that contained lots of loop branch instructions and reduce the resume time of stall pipeline by the miss prediction.

The need for modern processors is based on fast and precise branch predictors to improve the execution of instructions in the pipeline. In a parallel processor, the pipeline cannot execute the conditional instructions with the next clock cycle, leading to a pipeline stall. To address this issue, this paper suggests a variety of branch prediction techniques for improving the execution speed of conditional instructions. Firstly, a simple branch prediction and a dynamic branch prediction are applied to the trace files using saturating counters. Among these two, dynamic branch prediction provides better results by enhancing the accuracy rate of 2.01% than the static branch prediction. Further, the perceptron branch predictor predicts the implementation by using a table of perceptron and train function. This prediction scheme reduces the difficulties in dynamic branch predictor schemes such as reduces the complexity in history length table and improves the accuracy rate by 5.36%. For accuracy, a novel model based on global perceptron branch predictor is developed, which uses both global and per branch information. Trace-driven simulations have been performed by varying the range of hardware budget, traces file size, and the length of history register to increase the accuracy rate of each branch prediction technique. The obtained results suggest that the proposed global perceptron branch predictor provides an increased accuracy rate of 10.47% at 4 kb hardware budget and 8.06% at 4-bit history length than the perceptron branch predictor.

When CPU enters the era of instruction level parallelism, the execution cycle of instructions has become shorter and shorter. Meanwhile, the processing speed of CPU has become faster and faster. However, only from the execution process of CPU instructions, there is a key factor that limits the speed of CPU processing instructions, namely, the branch instruction processing. The branch predictor is used to predict the execution result of the current branch instruction (taken/non-taken), which can make the program counter get the target instruction to continue to execute according to the prediction result before calculating the target jump address. If the prediction is correct, it will greatly improve the execution efficiency of CPU. This paper starts from the two basic categories of static branch prediction and dynamic branch prediction. Then analyse their prediction principle, prediction accuracy and component consumption used for prediction. For static branch predictor, its hardware consumption is less than that of dynamic branch predictor, and its accuracy is also lower than that of dynamic branch predictor. Moreover, their shortcomings are pointed out in this paper. At last, based on the original branch predictor, better branch predictors developed in recent years are introduced. In the future, considering the hardware consumption, I think the development of branch predictor will continue to optimize the branch predictor combining global history and local history, from the number of stored entries, the correlation between branch instructions and so on. On the premise of executing a large number of instructions, every little improvement in the efficiency of the predictor will bring huge benefits.

This paper investigates how dynamic branch prediction in a microprocessor affects the predictability of execution time for software running on that processor. By means of experiments on a number of real processors employing various forms of branch prediction, we evaluate the impact of branch predictors on execution time predictability. The results indicate that dynamic branch predictors give a high and hard-to-predict variation in the execution time of even very simple loops, and that the execution time effects of branch mispredictions can be very large relative to the execution time of regular instructions. We have observed some cases where executing more iterations of a loop actually take less time than executing fewer iterations, due to the effect of dynamic branch predictors. We conclude that current dynamic branch predictions schemes are not suitable for use in real-time systems where execution time predictability is desired.

High-performance superscalar processors, which can be used in building base-stations of cell phones and cloud-based web servers, rely heavily on aggressive branch predictors to avoid stalls no matter the branch is taken or not. Dynamic branch predictor which is based on the historical records of the previously executed branches always outputs good performance. Two-bit predictor discussed in this paper is one of the most popular ones that always practically employed. This paper demonstrates two implementations of two-bit predictors. Using BTB to process solo conditional branches is the first one, which is normally used. Other categories of branch instructions may results in several bubbles as the penalty. While the other implementation employs BTB dealing with all kinds of branch instructions, generating target addresses without any delay cycle. Simulation results show that the second implementation has much better performance than the former one. It decreases the mis-prediction rate from 12.26% to 11.48%, and also has much higher prediction accuracy on indirect jumps. With these results, we have our predictor re-designed accordingly and implemented successfully in superscalar processors.

We evaluate the effects of guarded (or conditional, or predicated) execution on the performance of an instruction level parallel processor employing dynamic branch prediction. First, we assess the utility of guarded execution, both qualitatively and quantitatively, using a variety of application programs. Our assessment shows that guarded execution significantly increases the opportunities, for both compiler and dynamic hardware, to extract and exploit parallelism. However, existing methods of specifying guarded execution have several drawbacks that limit its use. Second, we study the interaction of guarded execution and dynamic branch prediction and show that the use of guarded execution significantly increases the number of instructions between mispredicted branches. Third, we propose a new method of specifying guarded execution. The proposed method uses special GUARD instructions, which can be used to incorporate guarded execution into existing instruction sets. GUARD instructions realize the full power of guarded execution, without the drawbacks of existing methods of specifying guarded execution.

Taking dynamic branch prediction into account in WCET determination turns out to be complex, particularly because of the possible interferences between branches. In this paper we argue the case for using static instead of dynamic branch prediction: the aliasing problem is swept away and, in many cases, the estimated worst-case numbers of branch mispredictions are reduced. We propose a method to predict each branch at compile time. Experimental results show how effective this approach can be.

In order to achieve an optimum performance of a given application on a given computer platform, a program developer or compiler must be aware of computer architecture parameters, including those related to branch predictors. Although dynamic branch predictors are designed with the aim of automatically adapting to changes in branch behavior during program execution, code optimizations based on the information about predictor structure can greatly increase overall program performance. Yet, exact predictor implementations are seldom made public, even though processor manuals provide valuable optimization tips.This paper presents an experimental flow with a series of microbenchmarks that determine the organization and size of a branch predictor using on‐chip performance monitoring registers. Such knowledge can be used either for manual code optimization or for design of new, more architecture‐aware compilers. Three examples illustrate how insight into exact branch predictor organization can be directly applied to code optimization. The proposed experimental flow is illustrated with microbenchmarks tuned for Intel Pentium III and Pentium 4 processors, although they can easily be adapted for other architectures. The described approach can also be used during processor design for performance evaluation of various branch predictor organizations and for testing and validation during implementation. Copyright © 2004 John Wiley & Sons, Ltd.

As fields like AI and robotics continue to expand, the demand for processors that are both powerful and energy-efficient is growing. This imposes the need for the development of such processors at a large scale and at a faster rate, which is possible through open-source development. While the current computing industry is dominated by proprietary technologies and licensed architectures, open-source hardware is rapidly gaining popularity across all industry segments, from high-performance computing to edge-IoT applications.This paper presents the design and FPGA implementation of a 32-bit five-stage pipelined processor core based on the RISC-V open-source Instruction Set Architecture (ISA). The proposed design presents a simple implementation of the RISC-V core, incorporating a 2-bit branch predictor. This makes it easier for beginners to understand the fundamental architecture of a pipelined RISC processor and branch predictors. Additionally, the design has considerable potential for future upgrades. The core is developed using SystemVerilog and has been tested through simulations in Verilator and Xsim, as well as by deploying it on a Basys3 FPGA board.

During the 1990s Two-level Adaptive Branch Predictors were developed to meet the requirement for accurate branch prediction in high-performance superscale processors. However, while two-level adaptive predictors achieve very high prediction rates, they tend to be very costly. In particular, the size of the second level Pattern History Table (PHT) increases exponentially as a function of history register length. Furthermore, many of the prediction counters in a PHT are never used; predictions are frequently generated from non-initialised counters and several branches may update the same counter, resulting in interference between branch predictions. In this paper, we propose a Cached Correlated Two-Level Branch Predictor in which the PHT is replaced by a Prediction Cache. Unlike a PHT, the Prediction Cache saves only relevant branch prediction information. Furthermore, predictions are never based on uninitialised entries and interference between branches is eliminated. We simulate three versions of our Cached Correlated Branch Predictors. The first predictor is based on global branch history information while the second is based on local branch history information. The third predictor exploits the ability of cached predictors to combine both global and local history information in a single predictor. We demonstrate that our predictors deliver higher accuracy than conventional predictors at a significantly lower cost.

Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintaining precise digital behavior on these devices grows more expensive with each technology generation. In some cases, replacing digital units with analog equivalents allows similar computation to be performed at higher speed and lower power. The units that can most easily benefit from this approach are those whose results do not have to be precise, such as various types of predictors. We introduce the Scaled Neural Predictor (SNP), a highly accurate prediction algorithm that is infeasible in a purely digital implementation, but can be implemented using analog circuitry. Our analog implementation, the Scaled Neural Analog Predictor (SNAP), uses current summation in place of the expensive digital dot-product computation required in neural predictors. We show that the analog predictor can outperform digital neural predictors because of the reduced cost, in power and latency, of the key computations. The SNAP circuit is able to produce an accuracy nearly equivalent to an infeasible digital neural predictor that requires 128 additions per prediction. The analog version, however, can run at 3GHz, with the analog portion of the prediction computation requiring approximately 7 milliwatts at a 45nm technology, which is small compared to the power required for the table lookups in this and conventional predictors.

Modern wide-issue superscalar processors tend to adopt deeper pipelines in order to attain high clock rates. This trend increases the number of on-the-fly instructions in processors and a mispredicted branch can result in substantial amounts of wasted work. In order to mitigate these wasted works, an accurate branch prediction is required for the high performance processors. In order to improve the prediction accuracy, we propose the bimode++ branch predictor. It is an enhanced version of the bimode branch predictor. Throughout execution from the start to the end of a program, some branch instructions have the same result at all times. These branches are defined as extremely biased branches. The bimode++ branch predictor is unique in predicting the output of an extremely biased branch with a simple hardware structure. In addition, the bimode++ branch predictor improves the accuracy using the refined indexing and a fusion function. Our experimental results with benchmarks from SpecFP, SpecINT, multi-media and server area show that the bimode++ branch predictor can reduce the misprediction rate by 13.2% to the bimode and by 32.5% to the gshare.

Previous branch prediction studies have relied primarily upon the SPECint89 and SPECint92 benchmarks for evaluation. Most of these benchmarks exercise a very small amount of code. As a consequence, the resources required by these schemes for accurate predictions of larger programs have not been clear. Moreover, many of these studies have simulated a very limited number of configurations. Here we report on simulations of a variety of branch prediction schemes using a set of relatively large benchmark programs that we believe to be more representative of likely system workloads. We have examined the sensitivity of these prediction schemes to variation in workload, in resources, and in design and configuration. We show that for predictors with small available resources, aliasing between distinct branches can have the dominant influence on prediction accuracy. For global history based schemes, such as GAs and gshare, aliasing in the predictor table can eliminate any advantage gained through inter branch correlation. For self-history based prediction scheme, such as PAs, it is aliasing in the buffer recording branch history, rather than the predictor table, that poses problems. Past studies have sometimes confused these effects and allocated resources incorrectly.

Correctly predicting the direction that branches will take is increasingly important in today's wide-issue computer architectures. The name program-based branch prediction is given to static branch prediction techniques that base their prediction on a program's structure. In this paper, we investigate a new approach to program-based branch prediction that uses a body of existing programs to predict the branch behavior in a new program. We call this approach to program-based branch prediction, evidence-based static prediction, or ESP. The main idea of ESP is that the behavior of a corpus of programs can be used to infer the behavior of new programs. In this paper, we use a neural network to map static features associated with each branch to the probability that the branch will be taken. ESP shows significant advantages over other prediction mechanisms. Specifically, it is a program-based technique, it is effective across a range of programming languages and programming styles, and it does not rely on the use of expert-defined heuristics. In this paper, we describe the application of ESP to the problem of branch prediction and compare our results to existing program-based branch predictors. We also investigate the applicability of ESP across computer architectures, programming languages, compilers, and run-time systems. Averaging over a body of 43 C and Fortran programs, ESP branch prediction results in a miss rate of 20%, as compared with the 25% miss rate obtained using the best existing program-based heuristics.

조건부 분기 명령어는 분기 벌칙을 야기함으로써 명령어 수준의 병렬도 향상에 제약을 가한다. 고성능 슈퍼스칼라 프로세서의 등장으로 인해, 정확한 분기 예측의 중요성은 더욱 높아지고, 이를 위해 동적 분기 예측의 일종인 2단계 적응적 분기 예측(2-level adaptive branch prediction) 방식이 개발되었다. 그러나 2단계 적응적 분기 예측이 상당히 높은 예측 정확도를 보여주고 있음에도 불구하고, 정확도에 따른 비용이 기하급수적으로 증가하는 등의 문제점을 가지고 있다. 본 논문에서는 2단계 적응적 분기 예측의 이러한 문제점을 개선하기 위하여 세트 연관 캐쉬를 이용한 캐쉬 상관 분기 예측기(cached correlated branch predictor)를 제안하고, 기존의 방식에 비해 예측의 정확도는 증가하고, 비용은 줄어든 것을 시뮬레이션을 통하여 확인한다. 세트 연관 예측기의 경우 전역과 지역 방식의 가장 좋은 예측 실패율은 각각 5.99%, 6.28%이며, 이는 종래의 2단계 적응적 분기 예측 방식에서의 가장 좋은 결과인 9.23%, 7.35%에 비해 각각 54%, 17% 향상된 결과이다. Conditional branches can severely limit the performance of instruction level parallelism by causing branch penalties. 2-level adaptive branch predictors were developed to get accurate branch prediction in high performance superscalar processors. Although 2 level adaptive branch predictors achieve very high prediction accuracy, they tend to be very costly. In this paper, set-associative cached correlated 2-level branch predictors are proposed to overcome the cost problem in conventional 2-level adaptive branch predictors. According to simulation results, cached correlated predictors deliver higher prediction accuracy than conventional predictors at a significantly lower cost. The best misprediction rates of global and local cached correlated predictors using set-associative caches are 5.99% and 6.28% respectively. They achieve 54% and 17% improvements over those of the conventional 2-level adaptive branch predictors.