E-beam to complement optical lithography for 1D layouts

We report a sub-30-nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology targeting the back end of line metal line patterning applications for logic nodes beyond 5 nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193-nm immersion SADP targeting a 40-nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, spin on carbon, spin on glass). The multicolor integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and, more generally, edge placement error as a whole for advanced process nodes. Unbiased line edge roughness (LER)/line width roughness (LWR) analysis comparison between EUV SADP and 193-nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open, and dielectric etch compared to 193-nm immersion SADP, the final process performance is matched in terms of LWR (1.08-nm 3 sigma unbiased) and is 6% higher than 193-nm immersion SADP for average unbiased LER. Using EUV, SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.

Lithographic scaling has been driven by improvements in wavelength and numerical aperture historically. In the semiconductor industry, the H2O base 192 immersion technique has still been main exposure tool combined with various low-k1 techniques, such like off-axis illumination, phase-shift mask and so on. The focus is now on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh′s definition. Actually, self-aligned spacer double patterning (SADP) has already been employed in high volume manufacturing of NAND flash memory devices. This paper introduces demonstration results focused on the extendibility of double patterning techniques for downward scaling and various device layouts utilizing SADP (Self-aligned Double patterning) mainly.

Pattern transfer by deep anisotropic etch is a well-established technique for fabrication of nanoscale devices and structures. For this technique to be effective, the resist material plays a key role and must have a high resolution, reasonable sensitivity, and high etch selectivity against the conventional silicon substrate or underlayer film. In this work, the lithographic performance of two high etch resistance materials was evaluated: ZEP520A (Nippon Zeon Co.) and mr-PosEBR (micro resist technology GmbH). Both materials are positive tone, polymer-based, and nonchemically amplified resists. Two exposure techniques were used: electron beam lithography (EBL) and extreme ultraviolet (EUV) lithography. These resists were originally designed for EBL patterning, where high quality patterning at sub-100 nm resolution was previously demonstrated. In the scope of this work, the authors also aim to validate their extendibility to EUV for high resolution and large area patterning. For this purpose, the same EBL process conditions were employed at EUV. The figures of merit, i.e., dose to clear, dose to size, and resolution, were obtained, and these results are discussed systematically. It was found that both materials are very fast at EUV (dose to clear lower than 12 mJ/cm2) and are capable of resolving dense lines/space arrays with a resolution of 25 nm half-pitch. The quality of patterns was also very good, and the sidewall roughness was below 6 nm. Interestingly, the general-purpose process used for EBL can be extended straightforwardly to EUV lithography with comparably high quality and yield. Our findings open new possibilities for lithographers who wish to devise novel fabrication schemes exploiting EUV for fabrication of nanostructures by deep etch pattern transfer.

Self-aligned double patterning (SADP) is being applied to 7nm technology node and below for back-end metal layers (routing layers) with pitches down to ~40nm. Unlike the traditional litho-etch-litho-etch (LELE) approach, SADP splits pitch using spacers whose 2nd pattern (Color-B) is self-aligned to its 1st pattern (Color-A). As a result, the SADP approach produces less variation than LELE approach by removing the second pattern misalignment on Si. Although SADP provides better overlay controllability than LELE, it still encounters many challenges. One of the challenges is controlling the 2nd patterning linewidth and uniformity. In general, the Color-B critical dimension (CD) has a larger variation than Color-A CD in the SADP process using Mandrel structure. In this paper, we investigate variations to the SADP Color-B CD based on self-aligned litho-etch litho-etch (SALELE) process flow, including the lithographic CD uniformity, hard mask etching, spacer etch and final Si etch. The corresponding contribution to Color-B CD variation is analyzed each step. After the major contributors to Color-B variation are identified, an experiment was designed to reduce Color-B pattern variation during the process. The silicon results show that compared with the old process condition, the new process can reduce Color-B variation significantly. With this new process, Color-B variation is comparable to Color-A variation.

Spatial phase-locked combination lithography for photonic crystal devices

Spatial phase-locked combination lithography for photonic crystal devices

Due to the unique electronic, optical, catalytic and biological properties, well ordered nanostructures have attracted enormous interest. They have potential applications in photonic crystal devices (Yablonovitch, 1987), large-density magnetic recording devices (Chou et al., 1994), novel electronic devices (Schmidt & Eberl, 2001), synthesis of DNA electrophoresis mediate (Volkmuth & Austin, 1992),nanocontainers (Chen et al., 2008), surface-plasmon resonance biosensors (Brolo et al., 2004), antireflective coatings for solar cells (Yae et al., 2005), and etc. Such broad applications of nanostructures were intimately associated with their unique properties, which are sensitively dependent on their size and/or shape. It is well-established that magnetic (Shi et al., 1996; Zhu et al.,2004), optical (Aizpurua et al., 2003; Larsson et al. 2007), electrocatalytic (Bratlie et al., 2007; Narayanan & El-Sayed, 2004), optoelectronic (Chovin et al., 2004), data storage (Ma, 2008), thermodynamic (Volokitin et al., 1996; Wang et al., 1998) and electrical transport (Andres et al., 1996; Bezryadin et al., 1997) properties of the nanostructures are affected by the shape and the size, as well as the interfeature spacing. In general, there are two approaches to realize ordered nanostructures with desired size, shape and arrangement. One is the “bottom up” approach on pre-patterned substrates (Zhong et al, 2007; Zhong et al., 2008). The other is the “top-down” approach (Ito & Okazaki, 2000). Both of these two approaches are always based on lithographic technology. In the first approach, lithographic techniques were employed to fabricate various patterned substrates, on which ordered nanostructures can then be realized by subsequent growth of desired materials. The main reason for this approach is to suppress defects in the nanostructures. In the second approach, ordered nanostructures can be directly fabricated by lithographic techniques. Several standard lithographic techniques are frequently exploited to fabricate desired surface nanostructures, including holographic lithography, electron-beam lithography (EBL) and ion-beam lithography (IBL) (Arshak et al., 2004;Ebbesen et al., 1998; Ito & Okazaki, 2000). Recently, a new extreme ultraviolet (EUV) lithography was developed, which is a potential candidate for achieving critical dimensions below 100 nm (Service, 2001). In addition, there are some other lithographic techniques applied in the fabrication of nanostructures (Haynes & Van Duyne, 2001). However, fabrication of nanostructures in a regular arrangement over large areas is still a major challenge in modern nanotechnologies. There is substantial interest in developing new technologies to facilitate pattern fabrication.

Self-Aligned-Double-Patterning (SADP) is a potential technology for metal layers in N10 and beyond nodes. SADP manufacturing process comes with lots of challenges. Several approaches were introduced to manufacture SADP. The most major SADP manufacturing approach is the Spacer-Is-Dielectric (SID). One of the main advantages of SADP over Litho-Etch-Litho-Etch (LELE) Double Patterning (DP) is better Mask Overlay Control. In addition, SADP results in better process tolerance and lower Line-Width Roughness. In this paper, we propose a model-based manufacturing flow for SID-SADP approach. The flow includes: (1) SADP Patterns Decomposition, (2) Etch Retargeting, (3) Sub Resolution Assist Features (SRAF) Insertion, (4) Optical Proximity Correction (OPC) process, and finally (5) Verification. The motivation beyond developing this flow is to find the least number of needed masks to achieve satisfactory imaging quality, and to characterize possible challenges in each step of the flow. Consequently, we highlight the challenges and the proposed techniques we examined to meet this objective.

Nano-patterns fabricated with extreme ultraviolet (EUV) or electron-beam (E-beam) lithography exhibit unexpected variations in size. This variation has been attributed to statistical fluctuations in the number of photons/electrons arriving at a given nano-region arising from shot-noise (SN). The SN varies inversely to the square root of a number of photons/electrons. For a fixed dosage, the SN is larger in EUV and E-beam lithographies than for traditional (193 nm) optical lithography. Bottom-up and top-down patterning approaches are combined to minimize the effects of shot noise in nano-hole patterning. Specifically, an amino-silane surfactant self-assembles on a silicon wafer that is subsequently spin-coated with a 100 nm film of a PMMA-based E-beam photoresist. Exposure to the E-beam and the subsequent development uncover the underlying surfactant film at the bottoms of the holes. Dipping the wafer in a suspension of negatively charged, citrate-capped, 20 nm gold nanoparticles (GNP) deposits one particle per hole. The exposed positively charged surfactant film in the hole electrostatically funnels the negatively charged nanoparticle to the center of an exposed hole, which permanently fixes the positional registry. Next, by heating near the glass transition temperature of the photoresist polymer, the photoresist film reflows and engulfs the nanoparticles. This process erases the holes affected by SN but leaves the deposited GNPs locked in place by strong electrostatic binding. Treatment with oxygen plasma exposes the GNPs by etching a thin layer of the photoresist. Wet-etching the exposed GNPs with a solution of I2/KI yields uniform holes located at the center of indentations patterned by E-beam lithography. The experiments presented show that the approach reduces the variation in the size of the holes caused by SN from 35% to below 10%. The method extends the patterning limits of transistor contact holes to below 20 nm.

Photolithography has been a driving force behind semiconductor scaling, but the technology has been at a standstill since the development of 193-nm water-based immersion lithography. As a consequence, the double patterning process has become the standard technology for diverse types of semiconductor devices as a means of extending the life of 193-nm exposure technology. We have previously reported on the extendibility and versatility of the double patterning process, from pitch-doubling by self-aligned double patterning (SADP)[1] to pitch-quadrupling by self-aligned quadruple patterning (SAQP)[2]. We also reported on the effectiveness of SADP technology for increasing resolution in hole patterns. While waiting for the development of extreme ultraviolet (EUV) lithography tools to be completed, it will be necessary to search out possibilities for further semiconductor scaling using the double patterning process as the mainstream technique for extending the life of 193-nm immersion lithography.

As process nodes continue to shrink, the semiconductor industry faces severe manufacturing challenges. Two most expected technologies may push the limits of next-generation lithography: extreme ultraviolet lithography (EUVL) and electron beam lithography (EBL). EUVL works by emitting intense beams of ultraviolet light that are reflected from a reflective mask into a resist for nanofabrication, while EBL scans focused beams of electrons to directly draw high-resolution feature patterns on a resist without employing any mask. Each of the two technologies encounters unique design challenges and requires solutions for a breakthrough. In this paper, we focus on the design-for-manufacturability issues for EUVL and EBL. We investigate the most critical design challenges of the two technologies, flare and shadowing effects for EUVL, and heating, stitching, fogging, and proximity effects for EBL. Preliminary solutions for these effects are explored, which can contribute to the continuing scaling of the CMOS technology. Finally, we provide future research directions for these key effects.

In this era, electronic devices such as mobile phones, computers, laptops, sensors, and many more have become a necessity in healthcare, for a pleasant lifestyle, and for carrying out tasks quickly and easily. Different types of temperature sensors, biosensors, photosensors, etc., have been developed to meet the necessities of people. All these devices have chips inside them fabricated using diodes, transistors, logic gates, and ICs. The patterning of the substrate which is used for the further development of these devices is done with the help of a technique known as lithography. In the present work, we have carried out a review on different types of lithographic techniques such as optical lithography, extreme ultraviolet lithography, electron beam lithography, X-ray lithography, and ion beam lithography. The evolution of these techniques with time and their application in device fabrication are discussed. The different exposure tools developed in the past decade to enhance the resolution of these devices are also discussed. Chemically amplified and non-chemically amplified resists with their bonding and thickness are discussed. Mask and maskless lithography techniques are discussed along with their merits and demerits. Device fabrication at micro and nano scale has been discussed. Advancements that can be made to improve the performance of these techniques are also suggested.

The capability for realizing high density nanostructures over large areas is important for the sensing of chemical and biological molecules based on localized surface plasmon resonance (LSPR) of metallic nanoparticles (Jensen et al., 1999; Barbillon et al., 2008; Faure et al., 2008). To characterize these plasmonic nanosensors on an area of∼ 100× 100 μm2 (Barbillon et al., 2009; Anker et al., 2008; Barbillon et al., 2008), extinction spectroscopy measurements are mainly used. In order to study multiple biomolecular interactions on the same surface, very large areas need to be fabricated. Various techniques such as focused ion beam lithography and electron beam lithography are available to design these large surfaces. However, these two techniques are slow to obtain these surfaces. Moreover, charge effect on insulating surface can alter the regularity of the pattern shape. Thus, these techniques will not be suitable for a large scale production. Other lithographic techniques such as extreme UV lithography are also used, but these techniques (fabrication of masks) are expensive and allow with difficulty to realize samples in small quantity. In addition, alternative methods emerged, and among these methods we find soft UV nanoimprint lithography (UV-NIL). The UV-NIL process is fast to realize high density nanostructures, not very expensive and compatible with biological and biochemical applications (Krauss & Chou, 1997). With UV-NIL, samples can be fabricated at room temperature and low pressure. A limiting factor of UV-NIL exists and this factor is the resolution of the fabricated molds (Jung et al., 2006; Austin et al., 2005). Flexible molds of the soft UV-NIL technique were fabricated by cast molding processes, in which an appropriate liquid mold material is deposited on a patterned master mold, followed by optical curing of the material. Moreover, a great homogeneity of patterns is obtained with soft UV-NIL on a large zone. Thus, the purpose of this chapter is to present in details the principle of soft UV-NIL and the results of plasmonic structure fabrication on glass substrates obtained by this technique in order to realize LSPR nanosensors for biological molecules. To finish, a plasmonic sensing of biomolecules is investigated in order to validate the use of soft UV-NIL.

DNA oligonucleotides of different sequences were patterned at the nanoscale. Areas of positive charge were generated by exposure of insulating substrates, spin-on hydrogen silsesquioxane or vapor-deposited SiO(2) on Si, with ionizing radiation sources used in electron beam and extreme ultraviolet lithography. Au nanoparticles (NPs) with a diameter of 15 nm, carrying covalently bound negatively charged single-stranded DNA oligonucleotides, were site specifically immobilized directly on the exposed regions and presented oligonucleotides for subsequent hybridization. Repeated exposure and deposition of NPs allowed for patterning multiple DNA sequences. Patterns with dimensions as small as 15 nm were fabricated using electron beam lithography. The use of DNA-functionalized NPs rather than just DNA facilitates metrology in scanning electron microscopy and improves the hybridization efficiency of the oligonucleotides on the surface.

Photolithography is a patterning process that uses light to transfer a pattern from a mask to a photosensitive polymer layer. The resulting pattern can either be etched into the underlying surface or used to define the patterning of a layer deposited onto the masked surface. This is essentially a two-dimensional process that can be repeated numerous times to fabricate various structures and devices. A classic use of these techniques is the fabrication of transistors on a silicon substrate as practiced in the semiconductor industry. Development over a number of years has yielded optimization of processing conditions, equipment, and materials to achieve ever smaller sized features and an increased density of integration. In the effort to fabricate even smaller (submicron to nanometer) features, other fabrication methods have also been developed such as electron beam lithography, focused ion beam lithography, and nanoimprint lithography. This chapter presents an introduction and practical approach to lithography and micromachining techniques in the context of MEMS device fabrication. The topics that are discussed here include: UV lithography, grayscale lithography, e-beam lithography, X-ray lithography, direct-write lithographies and imprint lithographies. A detailed description including highlighted examples of each of these lithographic techniques is presented in this chapter. At the end of the chapter a compilation of hands-on case studies is presented to assist readers in implementing these techniques in their own laboratories and developing custom fabrication capabilities that fulfill their own unique requirements.KeywordsInkjet PrintingNanoimprint LithographyNegative PhotoresistPDMS StampPhotoresist LayerThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.