Early detection of all-zero [formula omitted] blocks in High Efficiency Video Coding

Telehealth applications, such as remote diagnosis and examination, have become more and more popular nowadays. However, the generated large number of medical images and their impractical digital size when it comes to telehealth have brought pressure on communication infrastructures. More specifically, the image processing time has increased dramatically due to the size of the digitized images, while requiring substantial transmission bandwidth and storage space. For these reasons, medical image compression has become a hot research topic. While image compression techniques have evolved over several generations, it remains an open question how these standards will perform when it comes to sensitive oversized medical image content. In this paper, the emerging compression standard High Efficiency Video Coding (HEVC) and the next generation standard Versatile Video Coding (VVC) are evaluated on two different medical image datasets, covering the entire range of quality levels. The results of this study show that the VVC standard overperforms HEVC on raw medical image compression both visually and quantitatively, with the performance gap narrowing when dealing with pre-compressed medical images.

The growing popularity of high resolution video and the continuously increasing demands for high quality video on mobile devices are producing stronger needs for more efficient video encoder. Concerning these desires, HEVC, a newest video coding standard, has been developed by a joint team formed by ISO/IEO MPEG and ITU/T VCEG. Its design goal is to achieve a 50% compression gain over its predecessor H.264 with an equal or even higher perceptual video quality. Motion Estimation (ME) being as one of the most critical module in video coding contributes almost 50%-70% of computational complexity in the video encoder. This high consumption of the computational resources puts a limit on the performance of encoders, especially for full HD or ultra HD videos, in terms of coding speed, bit-rate and video quality. Thus the major part of this work concentrates on the computational complexity reduction and improvement of timing performance of motion estimation algorithms for HEVC standard. First, a new strategy to calculate the SAD (Sum of Absolute Difference) for motion estimation is designed based on the statistics on property of pixel data of video sequences. This statistics demonstrates the size relationship between the sum of two sets of pixels has a determined connection with the distribution of the size relationship between individual pixels from the two sets. Taking the advantage of this observation, only a small proportion of pixels is necessary to be involved in the SAD calculation. Simulations show that the amount of computations required in the full search algorithm is reduced by about 58% on average and up to 70% in the best case. Secondly, from the scope of parallelization an enhanced TZ search for HEVC is proposed using novel schemes of multiple MVPs (motion vector predictor) and shared MVP. Specifically, resorting to multiple MVPs the initial search process is performed in parallel at multiple search centers, and the ME processing engine for PUs within one CU are parallelized based on the MVP sharing scheme on CU (coding unit) level. Moreover, the SAD module for ME engine is also parallelly implemented for PU size of 32×32. Experiments indicate it achieves an appreciable improvement on the throughput and coding efficiency of the HEVC video encoder. In addition, the other part of this thesis is contributed to the VLSI architecture design for finding the first W maximum/minimum values targeting towards high speed and low hardware cost. The architecture based on the novel bit-wise AND scheme has only half of the area of the best reference solution and its critical path delay is comparable with other implementations. While the FPCG (full parallel comparison grid) architecture, which utilizes the optimized comparator-based structure, achieves 3.6 times faster on average on the speed and even 5.2 times faster at best comparing with the reference architectures. Finally the architecture using the partial sorting strategy reaches a good balance on the timing performance and area, which has a slightly lower or comparable speed with FPCG architecture and a acceptable hardware cost

The latest video coding standard High Efficiency Video Coding (HEVC) is developed by Joint Collaborative Team on Video Coding(JCTVC). HEVC can achieve better compression performance than any other coding standards, which adopts the quadtree structured coding tree unit (CTU). In encoding process, the CTU is recursively split into four equally sized coding unit (CU)s. Along with the multiple sizes of the CUs, the number of prediction unit(PU) modes has been largely increased, which raises the computational complexity in HEVC encoder greatly. In this paper, a fast inter mode decision algorithm based on motion estimation (ME) and texture feature is proposed to speed up the PU mode decision in HEVC encoder. Experimental results demonstrate that the overall algorithm that is proposed can save 41% encoding time on average while the decrease of coding quality is negligible, when compared to that of the HM10.0 reference software.

Scalable High efficiency Video Coding (SHVC) is the scalable extension of the latest video coding standard High Efficiency Video Coding (HEVC). One of the key novelties introduced by SHVC is that it enables hybrid codec scalability. This basically means that the video layers can be encoded with different video standards providing backward compatibility between codecs. In this paper, we propose a software parallel SHVC decoder in hybrid codec scalability configuration. The proposed design consists of an Advanced Video Coding (AVC) decoder for the Base Layer (BL) and a HEVC decoder for the Enhanced Layer (EL). In order to perform Inter Layer Prediction (ILP), a communication of decoding states and outputs is established between the two decoders. While the native frame based parallelism is still allowed within the two decoders, the proposed design also enables the use of frame based parallelism between the two decoders. The proposed software design enables a real time decoding of the HEVC EL at 2160p60 while the AVC base layer is decoded at 1080p60 for ×2 spatial scalability.

Cross residual transform for lossless intra-coding for HEVC

H.264/AVC is regarded as a popular video coding standard, and is widely used in multimedia applications. However, with an increasing demand for better quality videos, high efficiency video coding (HEVC) is all set to serve as the successor to H.264/AVC for higher resolution video applications. Since a majority of the multimedia devices have already been operating based on the H.264/AVC standard, it may not be worthwhile to completely replace the existing software and hardware components by different modules in order to adopt HEVC in such devices. Need is therefore felt to design a decoder for supporting H.264/AVC as well as HEVC, rather than attempting individual designs. This paper introduces a new dual‐standard deblocking filter architecture, which supports both H.264/AVC and HEVC standards. Algorithmic verification has been done in Matlab and then an appropriate VLSI architecture has been implemented on FPGA as well as in ASIC domain. The proposed architecture takes 26 clock cycles for H.264/AVC and 14 cycles for HEVC to complete the filtering of a 16 × 16 pixel block. It consumes 5.80 mW normalised power and occupies an area equivalent to 70.1k equivalent gate at frequency of 100 MHz. The proposed architecture takes 8.42 ms to filter the 4K ultra high definition (UHD) (3840 × 2160) frame in H.264 standard, and it takes 18 ms to filter the 8K UHD (7680 × 4320) frame in HEVC standard.

In the latest video coding standard high efficiency video coding (HEVC), a quadtree-based coding unit (CU) partitioning scheme is adopted to better adapt to the characteristics of the video contents. However, the flexible scheme significantly increases the coding complexity, because large amount of possible CU partitioning modes should be traversed. In this paper, we propose a two-stage fast inter CU decision method to reduce the coding complexity of the HEVC encoders. In Stage I, all the CUs are classified into three categories based on the Bayesian method after the prediction unit (PU) mode $merge\,\,2N\times 2N$ is checked. Early CU pruning and early CU skipping are then applied to two of the categories, respectively. For the remaining category which is difficult to differentiate by the rate-distortion cost of the PU mode $merge\,\,2N\times 2N$ , an early CU pruning scheme based on conditional random fields is performed in Stage II, which takes both the local characteristics of the current CU and the coding information of its neighboring CUs into consideration. Experimental results show that our method can reduce 54.93% and 45.84% of the coding complexity on average with only 1.19% and 1.03% Bjontegaard delta bitrate increment under the random access main and the low delay P configurations, respectively.

Nowadays, most of the video coding standards are based on the hybrid coding framework, whose information theoretic model was studied by Viswanathan and Berger more than ten years ago. The theoretic model, now known as the sequential coding model, abstracts consecutive frames as correlated random variables. Even the most efficient High Efficiency Video Coding (HEVC) standard can be roughly described by this sequential coding model. Searching for methods and algorithms which can improve the coding efficiency of HEVC is an attractive yet formidable task. In this paper, we propose a sequential coding model with backward refinement (BR). In this modified sequential coding model, after each frame is reconstructed, it can be backward refined by the frames encoded afterwards. Note that the proposed BR model does not depend on the coding tools and thus can be implemented on any current video coding standard. So, using this BR model, we can further improve the coding efficiency of any video coding standard, with only slight modification of the coding structure. Theoretical analysis is given on the performance of the BR model. We also propose a BR algorithm for the practical purpose, which is implemented on the HEVC standard. Experiment results show a maximum of 2.2% BD-rate saving compared with original HEVC codec.

Following the finalization of the state-of-the-art video compression standard High Efficiency Video Coding (HEVC) in 2013, there is a growing need for more compression efficiency to handle various new video services and formats. In order to address this need, the ITU-T and MPEG standardization bodies are working together in a Joint Video Expert Team (JVET) group on the standardization of a new video codec called Versatile Video Coding (VVC), aiming to achieve 50% bitrate reduction over HEVC by 2020. One of the solutions that can be proposed in the intra mode is increasing the number of prediction modes, thus allowing more efficient predictions and less energetic residues. However, this solution causes an increase in the signaling cost of the chosen mode, which counterbalances some of the gains obtained by the newly added prediction modes. To address this problem, we propose to derive prediction modes at the decoder, to avoid sending them in the bitstream. This is done by deriving the best prediction mode at the encoder through a gradient calculation performed on each pixel of a well-determined causal region of the image. This method is identically applied at the decoder, thus avoiding the intra mode signaling in the bitstream. This process defines a new coding mode named Decoder side Intra Mode Derivation (DIMD), which competes with other coding modes normally tested at the encoder, including the classical intra coding mode. The proposed method reduces, on average 0.3%, the bitrate used to encode a sequence configured in All Intra (AI), with limited additional decoding complexity (2%).

Implementing a reliable unequal error protection (UEP) technique based on motion activity of video frames is considered as an effective method to improve performance of compressed video bitstream transmitted over the wireless network. Most of the existing works are relevant to motion activity of H.264/advanced video coding frames. These mainly determine importance of frames based on either size of partitions having motion information or motion activity of their blocks. However, in the latest coding standard High Efficiency Video Coding (HEVC), there exists an improved block partitioning method, which demands a different representation of motion activity, especially for frames comprising a large number of units. This paper proposes motion density-based scheme of unequal error protection (UEP) for HEVC-compressed video bitstream. In comparison with previously motion activity-based UEP techniques, motion density has better capability to extract importance of the small-size units and consequently determines importance of frames. This is achieved by number of simulations conducted for the inter-prediction mode of the video bitstream.

Context-based adaptive binary arithmetic coding (CABAC) is a single entropy coding mode of the newest video coding standard, High Efficiency Video Coding (HEVC). Despite the high coding efficiency of CABAC, its data dependencies prevent effective parallelization, which also means limited throughput. Accordingly, during the HEVC standardization activity of entropy coding, both coding efficiency and throughput were considered. This paper highlights the key techniques that were proposed and adopted up to HEVC Draft International Standard (DIS). In addition, a new method is proposed for high throughput entropy coding. This method reduces the worst-case complexity of entropy coding without significant coding efficiency loss. From the experimental results, in terms of throughput improvement, we confirm that the proposed method reduces the number of context-coded bins up to 42.1 and 15.9 % on average.

In this paper, we design new efficient VLSI architecture for Integer Discrete Cosine Transform (DCT) included in the last new High Efficiency Video Coding (HEVC) standard. The proposed architecture has 4×4/8×8/16×16/32×32 Transform Units (TUs) operating in a parallel way to calculate two dimensional (2D) integer DCT using one block 1-D DCT and one transpose memory. Transform 1D is first calculated and the corresponding transform is stored in a memory. These stored data are secondly used to achieve the 2D DCT transform, using the same block for the first calculation for 1D. In addition, this architecture is based on shift and adder instead of the multiplication. The implementation was performed on the Xilinx Artix-7 (Zynq-7000) FPGA, the proposed accelerator hardware 2-D integer DCT takes 34421 slice LUTs, 8729 slice registers and the maximum achievable clock frequency for the proposed implementation is 289 Mhz. Finally, this design can be used to process the 30 frames for 8K video sequence and up to 120 frames per second for 4K.

Background: The emergence of new video applications and beyond high-definition formats (e.g.,4k×2k or 8k×4k resolution) signifies the need to develop a new video coding standard that is more sophisticated than other existing standards, including H.264/AVC. The new standard must have higher coding efficiency than that of H.264/AVC. High efficiency video coding (HEVC) has been designed to address all existing applications of H.264/MPEG-4 AVC and focus on suitability for high-level aplications. Method: In this study, we compared the new HEVC standardization and the previous version (H.264/AVC). The two encoders and the different tools and algorithms used were also comprehensively investigated. Finally, a comparison between software and hardware implementation was conducted. This study provides a relevant new hardware architecture for HEVC (H.265) using the existing one for H.264/AVC. Result: Experimental results show that H.265/MPEG-HEVC provides significant average bitrate savings of 40.3% and 35.4% for interactive and entertainment applications, respectively, compared with H.264/MPEG-AVC. Keywords: Video compression, embedded systeM, HEVC, H.264/AVC, video coding standards, video CODECs Syntax overview.

This paper reports on recent developments in video coding standardization, particularly focusing on the Call for Proposals (CfP) on video coding technology made jointly in January 2010 by ITU-T VCEG and ISO/IEC MPEG and the April 2010 responses to that Call. The new standardization initiative is referred to as High Efficiency Video Coding (HEVC) and its development has been undertaken by a new Joint Collaborative Team on Video Coding (JCT-VC) formed by the two organizations. The HEVC standard is intended to provide significantly better compression capability than the existing AVC (ITU-T H.264 | ISO/IEC MPEG-4 Part 10) standard. The results of the CfP are summarized, and the first steps towards the definition of the HEVC standard are described.

The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.