Edge coat applications in 3D memory processes

Abstract

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Wafer edge engineering is crucial in 3D memory process. Poor wafer edge integrity can lead to several issues. Film peeling in subsequent processes induced by severe wafer edge topography may become a defect source. Inadequate conductive film step coverage around the wafer edge can lead to etching or deposition arcing due to insufficient discharging pathways. Deeper etching requires longer etching time and higher etching power, both of which exacerbate the risk of arcing effects. To mitigate these challenges and maintain wafer edge integrity during 3D memory process, the application of various wafer edge treatments is essential. The methods include Negative Tone Development (NTD) with Wafer Edge Exposure (WEE) for wafer edge protection, film removal using dry or wet etching processes, selective wafer edge exposure, and edge coat. In this study, we optimized the edge coat process to achieve the desired coating width and thickness, ensuring its integration with 3D memory etching processes. Optical Microscope (OM) and Scanning Electron Microscope (SEM) were used to observe the condition of wafer edge and coating performance on wafer. Special efforts were made to minimize the hump height of the edge coat to meet the process requirements for tri-layer hard-mask applications in the etching process.