EEG data acquisition system 32 channels with relative power ratio based on Raspberry Pi 3

The prototype of the EEG (electroencephalogram) instrumentation systems has been developed based on 32-bit microcontrollers of Cortex-M3 ATSAM3X8E and Analog Front-End (AFE) ADS1299 (Texas Instruments, USA), and also consists of 16-channel dry-electrodes in the form of EEG head-caps. The ADS1299-AFE has been designed in a double-layer format PCB (Print Circuit Board) with daisy-chain configuration. The communication protocol of the prototype was based on SPI (Serial Peripheral Interface) and tested using USB SPI-Logic Analyzer Hantek4032L (Qingdao Hantek Electronic, China). The acquired data of the 16-channel from this prototype has been successfully transferred to a PC (Personal Computer) with accuracy greater than 91 %. The data acquisition system has been visualized with time-domain format in the multi-graph plotter, the frequency-domain based on FFT (Fast Fourier Transform) calculation, and also brain-mapping display of 16-channel. The GUI (Graphical User Interface) has been developed based on OpenBCI...

This study proposed a novel Field Programmable Gate Array (FPGA)-based 32-channel data acquisition system to acquire and process Electroencephalography (EEG) signal. The data acquisition system utilized PYNQ-Z1 board, which was equipped with a Xilinx ZYNQ XC7Z020-1CLG400C All Programmable System-on-Chip (APSoCs) that offered high performance embedded system because of the combination between the flexibility and versatility of the programmable logic (PL) and the high-speed embedded processor or programmable system (PS). As the core of the data acquisition system, the FPGA collected, processed, and stored the data based on Front-End Analog to Digital Converter (ADC) ADS1299EEG-FE. The communication protocol used in the data acquisition system was Serial Peripheral Interface (SPI) with daisy-chain configuration. For the signal processing part, a 5th-order Butterworth bandpass filter and Fast Fourier Transform (FFT) has been implemented directly on the PYNQ’s Overlay. The overlay was configurable FPGA design that extend the system from the PS of the ZYNQ to the PL, enabling us to control directly the hardware platform using Python running in the PS. The mean accuracy error obtained from validation result of the developed system was 1.34% and the Total Harmonic Distortion (THD) performance criterion resulting in 0.0091%, both of them validated with NETECH MiniSIM EEG Simulator 330. The comparison between the developed system and Neurostyle NS-EEG-D1 System acquiring the same EEG data shows correlation parameter gradient of 0.9818, y-intercept with -0.1803, and R squared of 0.9742 based on the least square analysis. The parameter above indicated that the developed system was adequate enough, if not on a par, with the commercialized, medical grade EEG data acquisition system Neurostyle NS-EEG-D1 as the system assured and maintained accuracy with higher sampling frequency.

Data acquisition (DAQ) system is developed for acquiring, processing and storing the tracking the position of the satellite. Tracking the spacecraft orientation and measuring actual position of satellite are done using inertial measurement unit (IMU). An IMU consists of three accelerometers and gyroscopes. Accelerometer measures the linear acceleration, and gyroscope measures angular velocity of the object that it is mounted on. Accelerometers along with gyroscopes form an integral part of satellite’s inertial guidance unit. Using DAQ system, the data can be measured from accelerometer or gyroscope or combination of both that can be used for space application. Designed DAQ system has accelerometer with Military Standard (MIL-STD) 1553 interface for data communication, to log the data without missing any of the samples at every 32 ms along with certain analog parameters in a deterministic way. Acquired acceleration data has to be converted to engineering units using numeric integration technique. This system display data in real time on the monitor and also store in a file for further off-line analysis. Hardware and software are developed using Arduino board along with MIL-STD-1553 protocol chip with serial peripheral interface (SPI), matrix laboratory (MATLAB) and Arduino IE, respectively.

DC motors are the most widely used electrical motors since their ease of use. Controlling a DC motor can be done by adjusting amount of voltage and current supplied to the motor. In this design the controlling is done using proportional integral derivative (PID) control, applied for movement in XY plane. Ziegler-Nichols method is used to determine PID constants. A Raspberry Pi is used to receive and process input from the user through a graphical user interface (GUI). The data input consists of two values, i.e. position and velocity. The GUI also shows the actual coordinate position on the screen. Two motors are controlled simultaneously by the Raspberry Pi through serial peripheral interface (SPI) with one microcontroller for each motor axis. The program contains a PID control algorithm to stabilize the motor speed. The coordination of the two stabilized motor speed is used to draw a sloping line. Sloping lines are drawn in order to determine the performance of the PID controller.

We evaluated the association between amygdalo-hippocampal complex (AHC) atrophy and two electroencephalography (EEG) markers of cognitive decline: increase of theta/gamma and increase of alpha3/alpha2 relative power ratio. Seventy-nine subjects with mild cognitive impairment (MCI) underwent EEG recording and magnetic resonance imaging scan. Based on the tertiles values of decreasing AHC volume, three groups of AHC growing atrophy were obtained. The groups were characterized by the performance to cognitive tests and theta/gamma and alpha3/alpha2 relative power ratio. AHC atrophy is associated with memory deficits as well as with increase of theta/gamma and alpha3/alpha2 ratio. Moreover, when the amygdalar and hippocampal volume are separately considered within AHC, the increase of theta/gamma ratio is best associated with amygdalar atrophy whereas alpha3/alpha2 ratio is best associated with hippocampal atrophy. AHC atrophy is associated with memory deficits and EEG markers of cognitive decline. So far, these EEG markers could have a prospective value in differential diagnosis between patients with MCI who develop dementia and those who do not as well as between MCI patients who will develop Alzheimer's disease and those who develop non-Alzheimer's disease dementias. The alterations of the functional connections, inducing global network pathological changes, in the whole AHC could better explain MCI state.

Research Article| March 01, 2016 The Internet of Geophysical Things: Raspberry Pi Enhanced REF TEK (RaPiER) System Integration and Evaluation Frank Sepulveda; Frank Sepulveda aDepartment of Geology, Baylor University, One Bear Place #97354, Waco, Texas 76798 U.S.A.frank_sepulveda@baylor.edu Search for other works by this author on: GSW Google Scholar Jay Pulliam Jay Pulliam aDepartment of Geology, Baylor University, One Bear Place #97354, Waco, Texas 76798 U.S.A.frank_sepulveda@baylor.edu Search for other works by this author on: GSW Google Scholar Author and Article Information Frank Sepulveda aDepartment of Geology, Baylor University, One Bear Place #97354, Waco, Texas 76798 U.S.A.frank_sepulveda@baylor.edu Jay Pulliam aDepartment of Geology, Baylor University, One Bear Place #97354, Waco, Texas 76798 U.S.A.frank_sepulveda@baylor.edu Publisher: Seismological Society of America First Online: 14 Jul 2017 Online Issn: 1938-2057 Print Issn: 0895-0695 © 2016 by the Seismological Society of America Seismological Research Letters (2016) 87 (2A): 345–357. https://doi.org/10.1785/0220150234 Article history First Online: 14 Jul 2017 Cite View This Citation Add to Citation Manager Share Icon Share Facebook Twitter LinkedIn MailTo Tools Icon Tools Get Permissions Search Site Citation Frank Sepulveda, Jay Pulliam; The Internet of Geophysical Things: Raspberry Pi Enhanced REF TEK (RaPiER) System Integration and Evaluation. Seismological Research Letters 2016;; 87 (2A): 345–357. doi: https://doi.org/10.1785/0220150234 Download citation file: Ris (Zotero) Refmanager EasyBib Bookends Mendeley Papers EndNote RefWorks BibTex toolbar search Search Dropdown Menu toolbar search search input Search input auto suggest filter your search All ContentBy SocietySeismological Research Letters Search Advanced Search ABSTRACT The proliferation of commercial Internet of Things (IoT) devices is raising consumers’ awareness of the benefits of enhancing everyday objects with the ability to communicate, sense, and process information. Commercial‐off‐the‐shelf (COTS) versions of the embedded technologies responsible for the rise of the IoT are easy‐to‐use, inexpensive, and relatively powerful. IoT Makers, technological do‐it‐yourself enthusiasts, utilize these technologies and the IoT ecosystem to create IoT devices that range from casual hobbyist to entrepreneurial in nature.In an effort to develop a “no‐engineer‐needed” Internet of Geophysical Things (IoGT) device, we integrated a COTS embedded computer with a geoscience‐related COTS data acquisition system (DAS). Using skills common to geoscientists, we integrated the Raspberry Pi System‐On‐Chip with the REF TEK (a Trimble brand) 130‐01 DAS. This Raspberry Pi enhanced REF TEK (RaPiER) provides IoGT Makers a platform for the development of geoscientific sensor node or network enhancements. IoGT Makers can use the RaPiER to tinker with IoT capabilities while simultaneously acquiring research‐quality data. Geoscientific (i.e., seismic) application areas that may benefit from RaPiER, particularly RaPiER nodal processing, include earthquake and engineering seismology.In this article, we discuss the emerging technologies that allow IoGT Makers to build their own IoGT device. We review our selection of the Raspberry Pi and REF TEK 130‐01 for IoGT device integration. We provide a RaPiER system integration guide and REF TEK interface software compiled for the Raspberry Pi ( available in the electronic supplement to this article). We present methods to expand RaPiER capabilities using the Raspberry Pi’s ecosystem. Last, we discuss our evaluation of RaPiER’s performance and its suitability for realistic field deployments. You do not have access to this content, please speak to your institutional administrator if you feel you should have access.

In this paper we report the characterizations results of serial peripheral interface (SPI) timing parameters for optical mouse sensor. SPI is an interface that facilitates the transfer of synchronous serial data. It supports two-way communication between mouse sensor and microcontroller. The test setups were used consist of digital oscilloscope, power supply, mouse sensor, test board and personal computer. The SPI timing parameters that were evaluated are read- address data delay, the timing between read and subsequent commands, rise and fall time, hold time, setup time, NCS to SCLK active, SCLK to NCS inactive (read operation) and SCLK to NCS inactive (write operation). The timing parameters results were within the limit as specified in product datasheet.

Serial Peripheral Interface (SPI) is a commonly used communication protocol that allows serial data transfer between a master and a slave device over a short distance. However, the current implementation of the Serial Peripheral Interface has a low speed and clock synchronization issue. When it comes to automotive, there a few things that are needed to be taken into consideration to increase the performance of the interface device. The paper present the design, simulation, verification and optimize SPI based on automotive interface device specifications. This includes a higher speed for the interface device and the efficiency of power dissipation. The SPI has been successfully optimized with a 1000MHz speed, a power of $575.7694 \mu \mathrm{W}$ and a total area of 1102.81mm2. The speed and area achieved are well improved over the current design of SPI. Even though the total dissipation achieved is above the current implemented SPI design, it is acceptable due to the technical relation between power and speed in VLSI design.

Synchronous serial interfaces are frequently employed to offer cost-effective board-level interfaces between various devices, including microcontrollers, DACs, ADCs, and others. Components that are compatible with SPI and Microwire are made by numerous IC makers. An interface called Serial Peripheral Interface (SPI) makes it easier to send synchronous serial data. In master/slave mode, data frames are initiated by the master device. With a separate slave choose line, multiple slave devices are permitted. It is necessary to guarantee that the given hardware design operates as intended and produces the desired outcomes. The design phases would need to be repeated after the functional flaws were discovered. Verification is thus a process that is time and money efficient. Due to this, a strong testbench structure is required, one that includes large broad verification elements that are easily extensible across designs and are extensively reusable. To gain good control over stimulus creation, functional coverage, and other factors, an industry standard verification technique is needed. The primary goal of this work is to design the Master SPI Core and use System Verilog to validate the code. Serial Peripheral Interface of symmetrical structure was synthesized using Cadence genus, and then simulated using Questa IDE. The testing of the SPI core was done by inserting the scan chains using the Cadence Genus tool and finally the code coverage of the SPI core was captured using the Questa IDE. Keywords: SPI, Coverage, Protocol, I2C, Functional Verification

This paper describes a monolithic integrated single-chip transceiver intended for impulse radio (IR) - Ultra-wide Band (UWB) applications compliant to the IEEE 802.15.4a standard. The transceiver operates in the higher UWB band on the mandatory channel #9 (7.9872 GHz). The implemented nominal data rate is 850 kb/sec. The presented chip consists of the entire RF-front-end, 6-bit-resolution successive approximation register (SAR) analogue-to-digital converter (ADC), and the baseband processor running with a clock of 31.2 MHz. The analogue frontend can be further segmented into a pulse generation and transmit part and a quadrature direct down conversion receiver part, whereas both parts share a frequency synthesizer based on an integer-N phase-locked loop (PLL). The impulse generation is based on the gated oscillator principle allowing required on-off keying (OOK) as well as binary phase shift keying (BPSK). While the receiver supports both, coherent and non-coherent impulse detection, here only non-coherent operation will be presented. The baseband processor part contains a separated 499.2 MHz clocked block for transmitter control and provides a serial peripheral interface (SPI) for data exchange with an external micro controller. The presented chip was fabricated in a 0.25 μm SiGe:C BiCMOS technology occupying a Si area of 3.25 - 3.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

The Serial Peripheral Interface (SPI) is a synchronous serial communication protocol commonly used in embedded systems, facilitating the connection between microcontrollers and peripheral devices such as sensors, displays, and memory. Traditional SPI hardware implementations often lack flexibility in clock frequency, clock polarity (CPOL), and clock phase (CPHA), limiting their adaptability in various applications and increasing development time and cost. To address these issues, this study designs and implements a configurable SPI module that can dynamically adjust parameters such as clock frequency, data bit width, CPOL, and CPHA through register control. The core of this design adopts a modular architecture that allows flexible configuration via register control, ensuring compatibility with different SPI modes and peripheral devices. Simulation tests have verified that the SPI module achieves the expected dynamic flexibility across multiple operation modes while ensuring communication accuracy and system stability.The configurable SPI module enhances the adaptability of embedded system communication protocols, reducing the need for hardware redesigns for specific applications. This register-based dynamic SPI design holds significant practical value in engineering applications and helps improve hardware development efficiency.

The current massive use of digital communications demands a secure link by using an embedded system (ES) with data encryption at the protocol level. The serial peripheral interface (SPI) protocol is commonly used by manufacturers of ESs and integrated circuits for applications in areas such as wired and wireless communications. We present the design and experimental implementation of a chaotic encryption and decryption algorithm applied to the SPI communication protocol. The design of the chaotic encryption algorithm along with its counterpart in the decryption is based on the chaotic Henon map and two methods for blur and permute (in combination with DNA sequences). The SPI protocol is configured in 16 bits to synchronize a transmitter and a receiver considering a symmetric key. Results are experimentally proved using two low-cost dsPIC microcontrollers as ESs. The SPI digital-to-analog converter is used to process, acquire, and reconstruct confidential messages based on its properties for digital signal processing. Finally, security of the cryptogram is proved by a statistical test. The digital processing capacity of the algorithm is validated by dsPIC microcontrollers.

CHAPTER 7 - Serial Peripheral Interface Bus Operation

Vibration monitoring is a measurement instrument used to identify, predict, and prevent failures in machine instruments[6]. This is very needed in the industrial applications, cause any problem with the equipment or plant translates into economical loss and they are mostly monitored component off-line[2]. In this research, a system has been developed to detect the malfunction of the components of Shimizu PS-128BT water pump machine, such as capacitor, bearing and impeller by online measurements. The malfunction components are detected by taking vibration data using a Micro-Electro-Mechanical System(MEMS)-based accelerometer that are acquired by using Raspberry Pi microcomputer and then the data are converted into the form of Relative Power Ratio(RPR). In this form the signal acquired from different components conditions have different patterns. The collected RPR used as the base of classification process for recognizing the damage components of the water pump that are conducted by Artificial Neural Network(ANN). Finally, the damage test result will be sent via text message using GSM module that are connected to Raspberry Pi microcomputer. The results, with several measurement readings, with each reading in 10 minutes duration for each different component conditions, all cases yield 100% of accuracies while in the case of defective capacitor yields 90% of accuracy.

This paper presents an incremental optical encoder based position and velocity measurements VLSI chip with a serial peripheral interface (SPI). It combines period and frequency countings to provide velocity estimates with good dynamic behavior over a wide speed range. By sensing the velocity of the encoder, it reserves the computational power of a supervisory microcontroller, and subsequently enhances the performance of the total system. Furthermore, multiple copies of the velocity encoder can access the behavior of multiple motors in parallel. It is compact with lower power consumption compared to traditional FPGA implementations. Although designed for use in the control unit of a medical robot with 34-axes and tight space and power constraints, it can be readily used in other applications. It is implemented in a 2P3M <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5μm</i> CMOS process and consumes 4.82mW power with active area of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.45mm²</i> .