Effects of FFT coefficient quantization on sinusoidal signal detection

Fast Fourier Transform (FFT) is critical in applications such as signal processing, communications, and AI. Embedded GPUs are often used to accelerate FFT due to their computational efficiency, but energy efficiency remains a key challenge due to power constraints. Existing solutions, such as the cuFFT library provided by NVIDIA, employ static configurations for the number of thread blocks and threads per block. This static approach often results in ineffective threads that consume power without contributing to performance, particularly if the FFT length or batch size varies. Furthermore, for large FFT lengths, cuFFT internally splits the computation into multiple kernel invocations. This decomposition can lead to L2 cache thrashing, resulting in redundant global memory accesses and degraded efficiency. To address these challenges, this paper proposes SSFFT, a software technique for embedded GPUs. The key idea of SSFFT is to maximize the number of useful threads that contribute to performance while minimizing ineffective threads. SSFFT is implemented based on a novel theoretical model that determines how many thread blocks and threads per block are effective for a given FFT length, batch size, and hardware resource availability. SSFFT statically determines these configurations and adaptively launches either a GPU kernel for regular FFT operations or a newly implemented kernel that integrates multiple FFT steps. By tailoring thread allocation to workload characteristics and minimizing inter-kernel memory interference, SSFFT improves energy efficiency without compromising performance. In our evaluation, SSFFT achieves a 1.29× speedup and a 1.26× improvement in throughput per watt compared to cuFFT.

A variable length Fast Fourier Transform (FFT) module is proposed in this paper, which can perform all the lengths of the Long Term Evolution (LTE) standard with high efficiency. Although the hardware complexity of the proposed scheme is slightly higher than the fix length FFT, it can implement the variable length FFT efficiently. Moreover, the proposed scheme can achieve a high throughput speed which satisfies the requirement of the real time orthogonal frequency division multiplexing (OFDM) signal processing for LTE system.

Radix-2 based fast Fourier transform (FFT) routines have been the main stream FFT that are commonly applied to the measurement and analysis of electric power system data. Because of the rigid sampling rates offered by most of the instrument manufacturers and the mathematical limitation imposed by the algorithm of radix-2 FFT, artificial post sampling data windows have been introduced to improve the utility of the radix-2 FFT. The 60 Hz and the 50 Hz based electrical power system frequencies are incompatible with the radix-2 FFT. There has been an ongoing search to adapt the FFT routine to the special requirements of electric power systems. Advances in the personal computer hardware has opened a new approach to perform the FFT via mixed radix routines. It offers greatly improved flexibility in the selection of a practical data size. This leads to the elimination of the need of the post sampling software windows. It also allows one to relax or eliminate the requirement of anti-aliasing measures for power system harmonic measurements.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fast Fourier Transform (FFT) is one of the core algorithms in digital signal processing. The traditional FFT processing method can no longer meet the data processing requirements, so the implementation and optimization of the better performance radix-4 FFT algorithm has very important research value. Based on FPGA technology, this paper proposes a design scheme of radix-4 FFT algorithm processing system. By optimizing the butterfly processing unit, the system realizes a high-performance FFT algorithm processing system with characteristics of faster operation speed, higher calculation accuracy, easy hardware implementation and large capacity compared with the traditional FFT processing method. It is well suited for scientific computing, image processing and other fields.

Fast Fourier Transform (FFT) operation is one of the most important fundamental operations in the digital signal processing systems.A new pipelined Radix-8 based Fast Fourier Transformation (FFT) architecture is designed for performing frequency transformation techniques.The objective of this design is to improve the speed and to reduce the area, delay and power.Radix-8 FFT, which is used to improve the speed of functioning by reducing the computational path.In the proposed new architecture named as -Radix-8 SDF FFT‖.In this architecture, the numbers of stages are reduced to 75%.The SDF FFT is to increasing the processing speed of architecture.The performance evaluation of Radix-8 SDF FFT architecture is determined through Very Large Scale Integration (VLSI) system design environment.In the VLSI system design, less area utilization, low power consumption and high speed are the main parameters.Hence, the main goal of proposed architecture is to reduce hardware complexity, power consumption and increasing both speed and throughput of the system.Applications:

FFT(Fast Fourier Transform) 알고리즘에는 DIT(Decimation-In-Time)와 DIF(Decimation-In-Frequency)가 있다. DIF 알고리즘은 Radix-2/4/8 등의 다양한 종류와 그 구현 방법이 개발되어 사용되고 잇으나, DIT 알고리즘은 순차적인 출력을 낼 수 있는 장점이 있음에도 불구하고 다양한 알고리즘이 연구되지 못하였다. 이 논문에서는 새로운 DIT Radix-4 FFT의 나비연산기(butterfly) 구조를 제안하고 검증하였다. 제안 구조를 사용하여 64-point FFT 구조를 설계하고 Verilog로 코딩하여 구현함으로써 제안 구조의 효용성을 입증하였다. 48개의 곱셈기를 사용하여 합성하였으며 678만 게이트 수를 나타내었다. 따라서 제안된 DIT Radix-4 FFT 구조는 순차적인 FFT 출력을 필요로 하는 OFDM 통신용 SoC(System on a Chip)에 사용될 수 있을 것이다. Two basic FFT(Fast Fourier Transform) algorithms are the DIT(Decimation-In-Time) and the DIF (Decimation-In-Frequency). In spite of the advantage of the DIT algorithm is to generate a sequential output, various structures have not been made. In this paper, a new DIT Radix-4 FFT butterfly structure are proposed and implemented using Verilog coding. Through synthesis, it is shown that the 64-point FFT is implemented by 6.78 million gates. Since the proposed FFT structure has the advantage of a sequential output, it can be used in OFDM communication SoC(System on a Chip) which need a high speed FFT output.

Fast Fourier Transform (FFT) is the most basic and essential part of Software Defined Radio (SDR). Therefore, designing regular, reconfigurable, modular and low hardware complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like DCT, DST etc. In this paper, the authors analyze implementation complexity and Noise to Signal Ratio (NSR) of Bruunpsilas FFT w.r.t. classical FFT for SDR. It is shown that, Bruunpsilas algorithm for FFT computation is ideally suited for SDR and should be used in preference over any classical FFT architecture for most practical cases.

This paper discuss about suitable damage size that should be detected by ultrasonic testing (UT) for nuclear power plant piping when consider about propagation of IGSCC. The power plant piping loop is inspected using UT as an in-service inspection (ISI). The reliability of UT result is affected by examination personnel. In this paper, the reliability of UT is defined simplified POD (Probability of detection) curve. The curve is defined by only three parameters, minimum detectable crack depth (a0), most detectable crack depth (a1) and maximum POD(m). The reliability of plant piping with different diameters are estimated by using this POD curve. The Failure probabilities were calculated with Monte Carlo approach. In case of low carbon stainless steel with IGSCC, a1 and m are less than 6 mm and 0.96 respectively, the piping loop failure probability is under 1x10-7. In another case of sensitized stainless steel with IGSCC, a1 and m are less than 6 mm and 0.96, the piping loop failure probability is under 1x10-3. It was found that the parameters of a1 and m do not affect plant reliability when a1 is between 3 to 6mm, and m is between 1.00 to 0.96. This result can be used to decide the requirement for examination personnel reliability.

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

A number of earlier publications discussed the benefits of probabilistic lifing in application to critical rotating engine components. One of the key random variables in both probabilistic and deterministic damage tolerant analysis is a probability of detection (POD) that represents a quantified Non-Destructive Evaluation (NDE) capability. The importance of having accurate POD information and its use in the probabilistic design and life management process is further promoted by the changing customer and regulatory requirements. New and existing FAA / EASA regulations and Air Force standards require damage tolerance analysis to be performed on critical engine components. POD for an NDE inspection is recognized as an important input for damage tolerance analysis. This information is needed for establishing and optimizing inspection schedules, calibrating life predictions, calculating fleet risk etc. Sensitivity of the above results to the accuracy of the POD curve, and to its approximation with a single point value (e.g. 90/50 POD = value of 90% probability with 50% confidence) will be discussed and illustrated with numerical examples. A brief overview of the methods for generating POD curves, and recent advancements in this area will be presented as well.

—The research on speech recognition systems currently focuses on the analysis of robust speech recognition systems. When the speech signals are combined with noise, the recognition system becomes distracted, struggling to identify the speech sounds. Therefore, the development of a robust speech recognition system continues to be carried out. The principle of a robust speech recognition system is to eliminate noise from the speech signals and restore the original information signals. In this paper, researchers conducted a frequency domain analysis on one stage of the Mel Frequency Cepstral Coefficients (MFCC) process, the Fast Fourier Transform (FFT), in children's speech recognition system. The FTT analysis in the feature extraction process determined the effect of frequency value characteristics utilized in the FFT output on the noise disruption. The analysis method was designed into three scenarios based on the value of the employed FFT points. The differences between scenarios were based on the number of shared FFT points. All FFT points were divided into four, three, and two parts in the first, second, and third scenarios, respectively. This study utilized children's speech data from the isolated TIDIGIT English digit corpus. As comparative data, the noise was added manually to simulate real-world conditions. The results showed that using a particular frequency portion following the scenario designed on MFCC affected the recognition system performance, which was relatively significant on the noisy speech data. The designed method in the scenario 3 (C1) version generated the highest accuracy, exceeded the accuracy of the conventional MFCC method. The average accuracy in the scenario 3 (C1) method increased by 1% more than all the tested noise types. Using various noise intensity values (SNR), the testing process indicates that scenario 3 (C1) generates a higher accuracy than conventional MFCC in all tested SNR values. It proves that the selection of specific frequency utilized in MFCC feature extraction significantly affects the recognition accuracy in a noisy speech.

It is still a big challenge to calculate the probability of defect detection for inspecting pits on austenitic stainless steel welding using traditional POD models. Because we determine the decision threshold, the POD curve has a lot of changes as the decision threshold changes, there is no clear reason to insist which threshold is reasonable. This study proposes a new probability of detection (POD) model to quantitatively assess the detection capability of eddy current probes for inspecting pits on austenitic stainless steel welding. The experimental results show that the proposed model is more reasonable than traditional ones. The novel POD model was employed to analyze three eddy current probes, uniform, TR, plus-point probes on austenitic stainless steel welding. The results reveal that the uniform eddy current probe has the best detection capability for inspecting pits on among the three probes.

This paper presents implementation of spectrometer based on off-the-shelf software defined radio (SDR) Ettus Research USRP X300 equipped with TwinRX daughterboard. Parallelized software, employing Fast Fourier Transform (FFT), is developed which allows two channel spectrum processing in real time with bandwidths up to 50[Formula: see text]MHz per channel, sample resolution of 14 bits and FFT lengths up to 32k points. Measured Allan stability time of the spectrometer is at least 750 sin laboratory environment. Software has network server-type interface that allows to conveniently integrate the spectrometer in radio telescope observation control and monitoring system with versatility of SDR allowing to implement various observation modes, for example, total power detection functionality with high frequency selectivity, which allows to carry continuum amplitude calibration in presence of near-by radio frequency interference. Presented spectrometer has been successfully integrated and used at RT-32 and RT-16 radio telescopes of Ventspils International Radio Astronomy Centre.

The split-radix approach for computing the discrete Fourier transform (DFT) is extended for the vector-radix fast Fourier transform (FFT) to two and higher dimensions. It is obtained by further splitting the (N/2*N/2) transforms with twiddle factors in the radix (2*2) FFT algorithm. The generalization of this split vector-radix FFT algorithm to higher radices and higher dimensions is also presented. By introducing a general approach for constructing the fast Hartley transform (FHT) from the corresponding FFT, new vector- and split-vector-radix FHT algorithms with the same desirable properties as their FFT counterparts are obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A method for objectively evaluating the defect detection performance of in-situ monitoring systems