Efficient Dataflow Software Pipelining

To the present day, the performance of microprocessors has progressed dramatically. Recently, almost all computer systems use reduced instruction set computer (RISC) architectures. However, about 30 years ago, complex instruction set computer (CISC) architectures were widely used for almost all computer systems. The advantages and successes of RISC architectures are attributable to their simplified structures. Conventional complex instruction set computer (CISC) architectures invariably included various and numerous instruction sets. Each instruction was able to execute a complicated multi-step operation. For that reason, the CISC architectures were useful in assembler-based programming environments and in systems with small amounts of memory. However, such complicated architectures prevent increases in clock frequency or a processor’s processing power. Therefore, RISC architectures—which use simple architectures based on single-step instruction sets—have been developed. The RISC architectures present advantages in terms of higher clock frequency, smaller implementation area, and lower power consumption than conventional complex instruction set computer (CISC) architectures. Observation of many examples reveals that, in circuit implementations, a simple structure is best to increase the overall performance. That principle is also applicable to programmable devices. If clock-by-clock reconfigurable devices are used, even a single instruction set computer (SISC) can be implemented onto them. A single instruction set computer is one in which a processor has only a single instruction. During production, various single instruction set computers are prepared: a single instruction set computer with an AND logic function, a single instruction set computer with an adder function, and so on. These processor units are implemented at necessary times and at necessary places of a programmable device. In CISC and RISC architectures, the hardware is fixed. Its operations are switched using software commands, as portrayed in Fig. 1(a). In contrast, in a single instruction set computer, the operation changes are executed by hardware reconfigurations, as shown in Figs. 1(b) and 1(c). Therefore, in a single instruction set computer, a processor with a certain function itself can be reconfigured to another processor with another function. The implementation of such single instruction set computers provides the following advantages under programmable device implementations. A single instruction set computer with the simplest architecture can operate at the highest clock frequency among all processor architectures. In RISC architectures, many selectors to change functions are implemented; such selectors have a certain delay. However, single instruction set computers

The evolution of computer architecture has given rise to two main approaches: RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer). These architectures differ significantly in terms of instruction design, efficiency, and performance. This study aims to analyze the performance and efficiency of RISC and CISC in the context of computer architecture organization. The methodology includes a literature review, comparative analysis, and performance evaluation based on parameters such as processing speed, power consumption, and design complexity. The results indicate that RISC tends to be more efficient in terms of power consumption and execution speed for simple instructions, while CISC excels in handling complex instructions with fewer lines of code. The findings of this study can serve as a reference for the development of modern computer architectures that balance performance and efficiency.

We describe a novel architectural framework that allows software applications written for a given Complex Instruction Set Computer (CISC) to migrate to a different, higher performance architecture, without a significant investment on the part of the application user or developer. The framework provides a hardware mechanism for seamless switching between two instruction sets, resulting in a machine that enhances application performance while keeping the same program behavior (from a user perspective). High execution speed on migrated applications is achieved through automated translation of the object code of one machine to that of the other, using advanced global optimization and scheduling techniques. Issues affecting application behavior, such as precise exceptions, as well as self-modifying code, are addressed. Relaxation of full compatibility on these issues lead to further possible performance gains, encouraging applications to adopt the newer architecture.The proposed framework offers a path for moving from complex instruction set computers (CISCs) to newer architectures, such as reduced instruction set computers (RISCs), superscalars, or very long instruction word (VLIW) machines, while protecting the extensive economic investment represented by existing software. To illustrate our approach, we show how system code written (and compiled) for the IBM System/390 can yield fine-grain parallelism, as it is targeted for execution by a VLIW machine, with encouraging performance results.

The single or one instruction set computer (OISC, pronounced, “whisk”) is the penultimate reduced instruction set computer (RISC)1. In OISC, the instruction set consists of one instruction, and then by the orthogonality of the instruction along with composition, a complete set of operations is synthesized. This approach is completely opposed to a complex instruction set computer (CISC), which incorporates many complex instructions as microprograms within the processor.

In this paper, we present the characterization and design of energy-efficient, on chip cache memories. The characterization of power dissipation in on-chip cache memories reveals that the memory peripheral interface circuits and bit array dissipate comparable power. To optimize performance and power in a processor's cache, a multidivided module (MDM) cache architecture is proposed to conserve energy in the bit array as well as the memory peripheral circuits. Compared to a conventional, nondivided, 16-kB cache, the latency and power of the MDM cache are reduced by a factor of 1.9 and 4.6, respectively. Based on the MDM cache architecture, the energy efficiency of the complete memory hierarchy is analyzed with respect to cache parameters in a multilevel processor cache design. This analysis was conducted by executing the SPECint92 benchmark programs with the miss ratios for reduced instruction set computer (RISC) and complex instruction set computer (CISC) machines.

12 - The next generations

1 - Complex instruction set computers

This paper presents the design and implementation of a pipelined 9-bit RISC Processor. The various blocks include the Fetch, Decode, Execute and Store result to implement 4 stage pipelining. Harvard Architecture is used which has distinct program memory space and data memory space. The only load and store is used to communicate with data memory. RISC using pipeline makes CPI as 1 and improves speed of execution. Verilog Language is used for coding purpose. The proposed architecture is then simulated using Modelsim. Reduced Instruction Set Computers (RISCs) are now use for all type of computational tasks. In the area of scientific computing, RISC workstations are being increasingly used for compute task such as DSP, DIP etc. RISC concepts help to achieve given levels of performance at significantly lower cost than other systems. Pipelined RISC improves speed and cost effectiveness over the ease of hardware description language programming and conservation of memory and RISC based designs will continue to grow in speed and ability. The main features of RISC processor are the instruction set can be hardwired to speed instruction execution. In the present work, the design of a 4-bit data width Reduced Instruction Set Computer (RISC) processor is presented. It has a complete instruction set, program and data memories, general purpose registers and a simple Arithmetical Logical Unit (ALU) for basic operations. In this design, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate load and store instructions access memory. The architecture supports 8 instructions to support Arithmetic, Logical, Shifting, and load -store operations. Verilog HDL has evolved as a standard hardware description language. A hardware descriptive language is a language used to describe a digital system. HDL's allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology- independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits. More recently Verilog is used as an input for synthesis programs which will generate a gate-level description for the circuit. The simulator which is used for the language is Xilinx ISE and Modelsim. Verilog is capable of describing simple behaviour. Machine cycle instructions allow the processor to handle several instructions at the same time. The processor can work at a high clock frequency and thus yields higher speed. This paper is about design of a simple RISC processor and synthesizing it. The RISC architecture follows single-cycle instruction execution.

This work presents the proof of concept implementation for the first hardware-based design of Moving Target Defense over IPv6 (MT6D) in full Register Transfer Level (RTL) logic, with future sights on an embedded Application-Specified Integrated Circuit (ASIC) implementation. Contributions are an IEEE 802.3 Ethernet stream-based in-line network packet processor with a specialized Complex Instruction Set Computer (CISC) instruction set architecture, RTL-based Network Time Protocol v4 synchronization, and a modular crypto engine. Traditional static network addressing allows attackers the incredible advantage of taking time to plan and execute attacks against a network. To counter, MT6D provides a network host obfuscation technique that offers network-based keyed access to specific hosts without altering existing network infrastructure and is an excellent technique for protecting the Internet of Things, IPv6 over Low Power Wireless Personal Area Networks, and high value globally routable IPv6 interfaces. This is done by crypto-graphically altering IPv6 network addresses every few seconds in a synchronous manner at all endpoints. A border gateway device can be used to intercept select packets to unobtrusively perform this action. Software driven implementations have posed many challenges, namely, constant code maintenance to remain compliant with all library and kernel dependencies, the need for a host computing platform, and less than optimal throughput. This work seeks to overcome these challenges in a lightweight system to be developed for practical wide deployment.

Complex instruction set computers (CISC) supply relatively sophisticated functions as part of the instruction set. This gives the programmer a variety of powerful instructions with which to build applications programs and even more powerful software tools, such as assemblers and compilers. In this way, CISC processors seek to reduce the programmer’s coding responsibility, increase execution speeds, and minimize memory usage.

Reduced instruction set computer (RISC) processors are built on the philosophy of eliminating complex instructions and of limiting the instruction set to only simple operations, thereby emphasizing fast execution. This approach has been adopted in many modern processors. Extending the RISC concept even further, we propose mono instruction set computer (MISC) architecture, which constrains the number of instructions on a processor to a single instruction. Because a MISC processor contains only a single instruction, in order to execute a variety of instructions, MISC processors must be implemented onto a programmable architecture and its configuration must be done frequently. Existing FPGAs can not achieve a high-performance MISC processor due to their long reconfiguration time. Therefore, we have been developing an optically reconfigurable gate array (ORGA) that supports high-speed dynamic reconfiguration. The ORGA can realize an ideal platform for MISC processors. In this research, we designed MISC processors based on RISC-V processor using the high-level hardware description language FSL. The design has been implemented onto an FPGA. This paper presents the evaluated results.

Reduced Instruction Set Computing (RISC) processors have wide selection of applications performance on speed and better cache memory. The advanced RISC microprocessors are extensively used for many of the complicated systems. Reduced Instruction set Computing (RISC) is a CPU (Central Processing Unit) design mechanism that displays fundamental instruction set and performs better after comparison with the other microprocessor architecture and has the ability to perform commands per instruction through microprocessor cycles. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. Building of a fully synthesizable 32-bit RISC processor with Fetching unit, Decoding unit, Data and instruction memory, and Execution unit. The RISC Processor design is synthesized and implemented using Xilinx ISE Tool and simulated using I-sim. A 32-bit RISC is simulated and checked through VIO IP cores. We can use debug feature to drive and monitor signals that are present on the real hardware. This work is intended with Verilog HDL and implemented with the help of development board using Artix-7 FPGA device. The outcomes of performance are evaluated in terms of area, timing performance and maximum frequency of operation. The RISC processor compares earlier comparable architecture with efficient developments.

Chapter 11 - The ARM Architecture

Register array processor

Omega - A RISC Architecture for Real-Time Applications