Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture

Parallelization of scalable elliptic curve cryptosystem processors in GF(2m)

This paper introduces the ECC (Elliptic Curve Cryptography) processor, in which the τ-NAF converter and Square-Square-Add Algorithm are utilized, for point multiplication on Koblitz curves. The proposed ECC processor operates over GF(2163). The τ-NAF converter can turn the complicated point double to simple point square, and the Square-Square-Add Algorithm can decrease the number of point addition. With the proposed design, the execution time for executing point multiplication will decrease by 21%, and the AT value (Area-Time product) will be lowered by 15% than the state-of-the-art design, which achieves better efficiency on the execution of ECC over Koblitz curves.

Wireless sensor networks (WSNs) are largely deployed in different sectors and applications, and Elliptic Curve Cryptography (ECC) is proven to be the most feasible PKC for WSN security. ECC is believed to provide same level of security such as RSA with a much shorter key length, and thus they seem to be ideal for applications with small resources such a sensor network, smartcard, RFID, etc. However, like any other cryptographic primitive, ECC implementations are vulnerable to Power Analysis Attacks (PAAs) that may reveal the secret keys by exploiting leaked power consumption from running cryptographic devices (e.g. smart cards, mobile phones etc.). In this paper, we present a comprehensive study of major PAAs and its countermeasures on ECC cryptosystems. In addition, this paper describes critical concerns to be considered in designing PAAs on ECC particular for WSNs, and illustrates the need to conduct, in the near future, intensive researches for the development of these specific PAAs.

The additional information (side effects) in Elliptic Curve Cryptography (ECC) hardware can be used to attack cryptographic systems. Additional information related to time, power consumption and electromagnetic radiation. Side channel attacks have been done with SPA (Simple Power Analysis), DPA (Differential Power Analysis), SEMA (Simple Electromagnetic Analysis) and DEMA (Differential Electromagnetic Analysis). Some scalar multiplication algorithm can be used to countermeasure SPA attack on elliptic curve cryptography. In this study, conducted experiments side-channel attacks ECC hardware implementations use binary algorithms by observing power consumption of ECC processor on FPGA. Experimental of side-channel attack is conducted to guess the secret key for data encryption and decryption by looking at the physical differences on hardware side effects. In this study, side-channel attack experimental is successful 100% get the key by analyzing of power consumption ECC processor.

SummaryThis workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art.

In this paper, a high-speed elliptic curve cryptography (ECC) processor specialized for primes recommended by the National Institute of Standards and Technology (NIST) was constructed. Toom-Cook multiplication without division was proposed to implement modular multiplication for NIST primes. Compared with a traditional algorithm, the computation complexity was reduced from 16 base multiplications to 7 in 4-way Toom-Cook multiplication. Moreover, we introduced non-least-positive (NLP) form into our design, so that the carry chain in the large array accumulation was broken down, which greatly shortened the critical path and made parallel processing possible. In order to support NLP form and lazy reduction strategy, conventional fast reduction methods for NIST primes were also modified. In addition, pipeline technique at the level of point multiplication was used, so the latency of modular inverse can be covered. Implemented on the Xilinx Virtex-6 FPGA platform, the ECC processor can perform a point multiplication every 54 μs at the cost of 30.3k LUTs and 48 DSPs. Synthesized with 180nm CMOS technology, the speed achieves 43.7 μs with 466k gate counts. These experimental results show a significantly better performance per area than previous works.

Developing a high-speed elliptic curve cryptographic (ECC) processor that performs fast point multiplication with low hardware utilization is a crucial demand in the fields of cryptography and network security. This paper presents field-programmable gate array (FPGA) implementation of a high-speed, low-area, side-channel attacks (SCAs) resistant ECC processor over a prime field. The processor supports 256-bit point multiplication on recently recommended twisted Edwards curve, namely, Edwards25519, which is used for a high-security digital signature scheme called Edwards curve digital signature algorithm (EdDSA). The paper proposes novel hardware architectures for point addition and point doubling operations on the twisted Edwards curve, where the processor takes only 516 and 1029 clock cycles to perform each point addition and point doubling, respectively. For a 256-bit key, the proposed ECC processor performs single point multiplication in 1.48 ms, running at a maximum clock frequency of 177.7 MHz in a cycle count of 262 650 with a throughput of 173.2 kbps, utilizing only 8873 slices on the Xilinx Virtex-7 FPGA platform, where the points are represented in projective coordinates. The implemented design is time-area-efficient as it offers fast scalar multiplication with low hardware utilization without compromising the security level.

Power analysis attacks have emerged as a significant threat to the security of elliptic curve cryptography (ECC), necessitating the development of countermeasures that can safeguard against such attacks without compromising computational efficiency. This paper introduces an innovative approach that integrates signed factorial expansions (SFE) with random masking techniques for scalar multiplication, a critical operation in ECC. The proposed method encodes large scalar values into smaller integers and incorporates randomization to resist a variety of power analysis attacks effectively. By conducting simulations, we demonstrate that the algorithm not only maintains high computational efficiency but also exhibits excellent performance in resource-constrained cryptographic chips, which are typically vulnerable to such attacks. The algorithm's resilience is attributed to the randomization of scalar multiplication operations, which obscures the correlation between operation and power consumption, thereby thwarting attempts at key recovery by an attacker. Our simulation results validate the algorithm's ability to defend against simple power analysis (SPA), differential power analysis (DPA), zero-value register-based power analysis (RPA), zero-value point-based power analysis (ZPA), and double attack (DA) methods. This work not only enhances the security of ECC implementations but also provides a practical solution for cryptographic systems with limited resources, offering a promising direction for future research and applications in the field of cryptography.

A dual-core high-performance processor for Elliptic Curve Cryptography (ECC) in GF( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> ) over Generic Weierstrass Curves was presented in this brief. Firstly, an optimized radix-128 Montgomery modular multiplication algorithm was proposed. It takes 6 clock cycles to calculate modular multiplication, which promotes the speed of elliptic curve point-addition (PA) and elliptic curve point-doubling (PD). Secondly, a dual-core hardware architecture which includes PD core and PA core to calculate elliptic curve point-multiplication (PM) was developed. It can speed up the PM by adopting parallelism with different levels and optimizing the scheduling. Finally, a data transfer architecture between PA and PD cores was proposed which requires only a 1024-bit register. It improves the speed of PM. The proposed design consumes 996k gates and compute the PM in 0.017 ms on ASIC with a 90 nm standard cell library. Moreover, the proposed design is also implemented on FPGA (Virtex-6 platform), which consumes 182k LUTs and compute the PM in 0.056 ms.

Embedded systems support more and more features. Authentication and confidentiality are part of them. These systems have limitations that put the public-key RSA algorithm at a disadvantage: Elliptic curve cryptography (ECC) becomes more attractive because it requires less energy and less area. A lot of attacks exploit physical access on cryptographic hardware device: power analysis attacks (SPA, DPA), or timing analysis attacks. The coprocessor presented here supports all critical operations of an ECC cryptosystem and has been secured against side channel attacks.

Elliptic curve cryptography (ECC) is based in one of the hardest arithmetic problems, the elliptic curve discrete logarithm problem, making ECC a reliable cryptographic technique. In addition to this advantage, ECC requires shorter keys compared to other public key algorithms, which suggests its use in low-end systems such as smart cards because of its efficiency and limited hardware requirements. Currently the leading smart card technology is Java card. Though both Java 2 standard edition (J2SE) 5.0 and Java card (JC) 2.2.1 include classes and interfaces making ECC available to Java programs, they are not complete, making it necessary to use additional, non-standard packages if the programmer wants to use ECC for different operations (digital signature, data encryption and decryption, etc.). In the present work, we provide a complete review of the state of the art of ECC in J2SE and Java card, with a complete list of operations available in both standard implementations and proprietary packages.

Cryptographic System-on-Chips (SoCs) are becoming more and more popular. In these systems, cryptographic accelerators are integrated with processor cores to provide users with the software&#x2019;s flexibility and hardware&#x2019;s high performance. First, this work aimed to confirm the vulnerability of cryptographic SoCs against several types of power analysis attacks. Then, the novel Random Dynamic Frequency Scaling (RDFS) countermeasure is proposed to improve the resistance of such systems. The proposed RDFS countermeasure improved the power analysis resistance while maintaining low-performance overhead and hardware costs by generating more than 219,000 distinct frequencies for driving only the cryptographic accelerators. The effectiveness of the proposed RDFS countermeasure is demonstrated by conducting realistic Correlation Power Analysis (CPA) attacks, Deep-Learning-based Side-Channel Analysis (DL-SCA) attacks, and Test Vector Leakage Assessment (TVLA) testing methodology. The experimental results show that the RISC-V SoC protected by RDFS countermeasure can withstand CPA attacks and TVLA test with more than five million power traces, which is the best result compared to other related works. The proposed RDFS countermeasure also harden the targeted RISC-V SoC&#x2019;s resistance against DL-SCA attacks.

Embedded wireless devices require secure high-performance cryptography in addition to low-cost and low-energy dissipation. This paper presents for the first time a design methodology for security on a VLIW complex DSP-embedded processor core. Elliptic curve cryptography is used to demonstrate the design for security methodology. Results are verified with real dynamic power measurements and show that compared to previous research a 79% improvement in performance is achieved. Modification of power traces are performed to resist simple power analysis attack with up to 39% overhead in performance, up to 49% overheads in energy dissipation, and up to 11% overhead in code size. Simple power analysis on the VLIW DSP core is shown to be more correlated to routine ordering than individual instructions. For the first time, differential power analysis results on a VLIW using real power measurements are presented. Results show that the processor instruction level parallelism and large bus size contribute in making differential power analysis attacks extremely difficult. This research is important for industry since efficient yet secure cryptography is crucial for wireless communication devices.

To ensure secure information exchange, demand for hardware implementation of elliptic curve cryptography (ECC) is increasing rapidly in recent years. In this paper, we propose an ASIC design for ECC over SCA-256 prime field, delivering both high performance and great SPA resistance. For algorithm selection, we integrate calculation simplification into the classic algorithm, Montgomery Powering Ladder (MPL). Based on the deduction of Fast NIST Reduction, we innovatively achieve the configurable modular multiplication module and then the isochronous point addition and double units. Pipeline architecture, execution order optimization and modular design are all applied to improved performance. Evaluated by CMOS standard cell library of 0.13 \(\upmu \)m, this ECC processor costs only 208 \(\upmu \)s and 6.8 \(\upmu \)J for one scalar multiplication and runs at high frequency of 228 MHz with area of 156 k gates. Compared to related works, it is much more advantageous in not only area-time product but also SPA resistant protection.

Comb method is an efficient method to calculate point multiplication in elliptic curve cryptography, but vulnerable to power-analysis attacks. Various algorithms have been proposed recently to make the comb method secure to power-analysis attacks. In this paper, we present an efficient comb method and its Simple Power Analysis (SPA)-resistant counterpart. We first present a novel comb recoding algorithm which converts an integer to a sequence of signed, MSB-set comb bit-columns. Using this recoding algorithm, the signed MSB-set comb method and a modified, SPA-resistant version are then presented. Measures and precautions to make the proposed SPA-resistant comb method resist all power-analysis attacks are also discussed, along with performance comparison with other comb methods. We conclude that our comb methods are among the most efficient comb methods in terms of number of precomputed points and computational complexity.KeywordsElliptic CurveElliptic CurfPoint AdditionEvaluation StageElliptic Curve CryptographyThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.