Efficient TCAM Rules Distribution Algorithms in Software-Defined Networking

Packet classification based on rules of packet header fields is the key technology for enabling software-defined networking (SDN). Ternary content addressable memory (TCAM) is a widely used hardware for packet classification; however, commercially available TCAM chips have only limited storage. As the number of supported header fields in SDN increases, the number of supported rules in a TCAM chip is reduced. In this work, we present a novel scheme to enable packet classification using TCAM with entries that are narrower than rules by storing the most representative field of a ruleset in TCAM. Due to the fact that not all rules can be distinguished using one field, our scheme employs a TCAM-based multimatch packet classification technique to ensure correctness. We further develop approaches to reduce redundant TCAM accesses for multimatch packet classification. Although our scheme requires additional TCAM accesses, it supports packet classification upon long rules with narrow TCAM entries, and drastically reduces the required TCAM storage. Our experimental results show that our scheme requires a moderate number of additional TCAM accesses and consumes much less storage compared to the basic TCAM-based packet classification. Thus, it can provide the required scalability for long rules required by potential applications of SDN.

Using packet classifier algorithms in packet processing network systems is the key idea to process packets rapidly. These algorithms are so important, especially in processor equipments used in internet backbones. Ternary content addressable memories (TCAM) are used to do parallel search in hardware implementation of these algorithms. Despite the accessibility of high-speed search, one of main problems to use TCAM is its high consumption power supply. In this study, a new technique is provided to reduce memory consumption in TCAM blocks which are used in hardware classifier. In classifier architecture, first, decision tree is created and classifier rules are distributed among its leaf nodes. Since each leaf of the tree corresponds to one TCAM block, rules are included in different blocks of TCAM corresponding to tree structure, in the second stage. In this architecture, a supplementary TCAM block is used as the general block. Recent architectures have encountered memory waste and a considerable increase in power consumption due to unbalanced distribution of rules in main TCAM blocks and unexpected increase in the number of repeated rules in the general block. In this study, a new algorithm is offered to optimize rule distribution in TCAM blocks in the first stage of packet classification. Efficiency of the proposed architecture which uses intelligent cuts has been compared with recent architectures. Comparing results shows that the proposed method can distribute rules in TCAM block more balanced than competitor architectures and at the same time, reduce the number of rules assigned to the general TCAM block.

Ternary content addressable memory (TCAM) is a key component in various digital systems due to its fast lookup operation. Symmetric and asymmetric TCAM cells are two widely used cells for implementing a TCAM array. This paper presents several comparison fault models of TCAMs with asymmetric cells based on electrical defects. Some new comparison faults which do not exist in a TCAM with symmetric cells are found. One march-like test algorithm TAC-H is also proposed to cover the defined comparison faults. The TAC-H consists of 8N Write operations and (3N + 2B) Compare operations for an N × B-bit TCAM with Hit output only. We also propose two march-like diagnosis algorithms to identify the defined comparison faults of TCAMs with asymmetric cells. The first diagnosis algorithm DAC-H requires 5N Write operations, 3N Erase operations, and (5N + 2B) Compare operations to distinguish 100 percent comparison faults for a TCAM with Hit output only. The second diagnosis algorithm DAC-P requires 3N Write operations, 1N Erase operations, and (5N + 2B) Compare operations to distinguish 100 percent comparison faults for a TCAM with Hit and priority address encoder outputs.

Ternary Content Addressable Memory (TCAM) is widely used in network infrastructure for various search functions. There has been a growing interest in implementing TCAM using reconfigurable hardware such as Field Programmable Gate Array (FPGA). Most of existing FPGA-based TCAM designs are based on brute-force implementations, which result in inefficient on-chip resource usage. As a result, existing designs support only a small TCAM size even with large FPGA devices. They also suffer from significant throughput degradation in implementing a large TCAM, mainly caused by deep priority encoding. This paper presents a scalable random access memory (RAM)-based TCAM architecture aiming for efficient implementation on state-of-the-art FPGAs. We give a formal study on RAM-based TCAM to unveil the ideas and the algorithms behind it. To conquer the timing challenge, we propose a modular architecture consisting of arrays of small-size RAM-based TCAM units. After decoupling the update logic from each unit, the modular architecture allows us to share each update engine among multiple units. This leads to resource saving. The capability of explicit range matching is also offered to avoid range-to-ternary conversion for search functions that require range matching. Implementation on a Xilinx Virtex 7 FPGA shows that our design can support a large TCAM of up to 2.4 Mbits while sustaining high throughput of 150 million packets per second. The resource usage scales linearly with the TCAM size. The architecture is configurable, allowing various performance trade-offs to be exploited. To the best of our knowledge, this is the first FPGA design that implements a TCAM larger than 1 Mbits.

Thanks to its 1-cycle lookup performance, the Ternary Content Addressable Memory (TCAM) is considered an essential hardware component for the deployment of high-performance Software-Defined Networks (SDN). Unfortunately, in many network scenarios, TCAMs can quickly fill due to their limited memory size, thus preventing the installation of new flow-rules and leading to inefficient traffic forwarding. This issue has already been addressed in computer programming, where Virtual Memory is offered to applications to mimic a much larger physical memory, by swapping memory pages to disk. In a previous work, we proposed and discussed the architecture of a Memory Management System (MMS) for SDN controllers that, like the analogous process for computer Operating Systems, optimizes the memory usage and prevents anomalies due to lack of memory space. This work proposes a memory swapping mechanism for SDN controllers, a function of the MMS which gives SDN applications the illusion of unlimited memory space in the forwarding devices, without requiring any hardware modification or changes in the control protocol. The paper discusses the memory swapping mechanism design, its implementation and proves its quality using real traffic traces, demonstrating lower TCAM memory utilization and potentially increased network performance in terms of end-to-end throughput. A prototype of the MMS is available for testing as an open source project.

TCAM space-efficient routing in a software defined network

The speed requirement for the routing table lookup and the packet classification is rapidly increasing due to the increase in the number of packets needed to be processed per second. The hardware-based packet classification relies on ternary content addressable memory (TCAM) to meet this speed requirement. However, TCAM consumes huge power and also supports only for longest prefix match and exact match, where the classification rule also has a range match (RM) field. Hence, it is mandatory to encode the RM into prefix match to accommodate the rule in TCAM. In the worst case, one rule is encoded into (2 W -2) 2 rules (where W is a number of bits to represent range). This work proposes a novel RM architecture, and a detailed analysis about the range field on the standard dataset and the real-life classifier rules are presented. In the literature, the existing RM architecture is used to avoid the range to prefix conversion, but due to the serial operation, it lacks in performance. For constant time lookup, TCAM is the best option, but it does not support RM. The proposed architecture takes one clock cycle for RM and does not require any encoding/ conversion. Hence, there will be a single entry for every rule. It is observed that just 4% of the two-dimensional range rules are present in this dataset, and it will increase the rule set size by 4 times in the best case and nearly 30 times in the worst case. The proposed RM circuit is operated in parallel with TCAM without compromising the speed, and this circuit saves huge power around 70% and area around 61%, where the range to prefix conversion/encoding is completely avoided. The proposed architecture is well suited for current IPv4- and IPv6-based networks, as well as in software-defined networks in the near future.

Memory which is used for searching applications, like Network routers, operating at a higher speed is called Ternary Content Addressable Memory (TCAM). The requirement of TCAM is gradually growing in the searching field applications. TCAM memories are usually built in ASIC (Application Specific Integrated Circuit) which offers searching operation at a higher speed in a predetermined time but is expensive in cost. TCAMs designed on FPGAs (Field Programmable Gate Array) experience high power consumption, larger use of FPGA resources, and suffer from the inefficiency of storage. TCAM using multipumping and multiported SRAM is designed for achieving an effectual use of FPGA resources, and a reduction in usage of power and area. In the present SRAM based TCAM designs, there is an exponential growth in memory usage due to the increase in the patterns of TCAM, which is reduced by cascading the multiple blocks of SRAM (BRAMs) in FPGA that makes growth linear. BRAMs of FPGAs have restrictions in depth, which restricts the effectual storage of TCAM bits. In this paper, a modified TCAM design is proposed which avoids this restriction by using shallow sub-blocking of BRAMs. The design proposed in this paper operates the multiported SRAM by using the dual-port BRAM and by clocking it internally at a higher frequency using multipumping technique which allows access of the BRAM subblocks in one cycle of the system clock. These modifications in the divisional traditional TCAM table results in an effectual design of TCAM memory. The proposed design is coded in Verilog and simulated using the Xilinx ISE tool and was implemented on a Virtex 7xc7vx485 FPGA device. The proposed design has better performance, in terms of 26% reduction in power and 7% reduction in area, as compared to existing SRAM based TCAM design.

Ternary Content Addressable memory (TCAM) is widely used in wireless net, image processing, data compression, etc. where high-speed data search is required. Despite using faster matching algorithms, software search remains much slower than TCAM based hardware searches. In this paper, we propose a high-speed 11 transistors (11-T) TCAM with significant improvement in speed and power compared to the existing 18-T TCAM and 9-T quasi-static TCAM. Results have been verified via Spice simulations performed using UMC 28-nm technology for a $16 \times 16$ TCAM array. Results show that the proposed 11-T TCAM is 21% and 10$\times$ faster than its counterpart 9-T and 18-T TCAM respectively. The proposed 11-T TCAM consumes 30% and 1.5 % less energy for a word search operation in a $6 \times 16$ array compared to the existing 9-T TCAM and 18-T TCAM respectively.

Ternary content addressable memory (TCAM) are widely used for their high speed search operation. However, TCAMs have larger area and power consumption. The use of advanced technology nodes and emerging non-volatile devices can improve the same. In this paper, magnetic tunnel junction (MTJ), which is a non-volatile device is used to reduces the overall power consumption of TCAM by realizing zero standby power. A novel Verilog-A model of MTJ which is suitable for SOI technology was developed. The conventional NOR and NAND type TCAM cells, and two MTJ based hybrid TCAM cells are constructed using 45 nm RF-SOI technology node. The proposed cells use only one transistor for precharge. The simulation results show that the NOR and NAND type TCAM cells consumes 29.11 μW and 19.33 μW of power respectively. The MTJ based TCAM cells consume 7.33 μW and 8.58 μW of power which is about 70% and 63% lower compared to the NAND and NOR TCAM cells.

Ternary Content Addressable Memory (TCAM) is widely used for caching flow entries in Software Defined Network (SDN). However, limited by the current technology level and hardware cost, the capacity of TCAM is difficult to meet the needs for caching flow entries of large scale SDN, which would seriously affect the scalability of SDN. Aimed at the problem, some researches improve the efficiency of TCAM capacity by setting different lifecycle for different flow entries. Such as Openflow protocol proposed the default flow entry lifecycle, AHTM scheme dynamicly adjusted flow entry lifecycle according to the number of interrupted flows. However, these schemes didn't consider the dynamic features of network traffic in SDN, and hardly conform to the actual network demands. In order to effectively utilize TCAM capacity and thus enhance the scalability of SDN, we propose TF-IdleTimeout scheme to dynamically set flow entry lifecycle according to real-time network traffic in SDN-based data center network. Two criterion, called Flow Entry Missing Number and Flow Dropping Number, are used to evaluate the effect. The results show that, compared with existing schemes, TF-IdleTimeout scheme can greatly improve the utilization efficiency of TCAM capacity in SDN.

Memory-based computing using associative memory has emerged as a promising solution to reduce the energy consumption of important classes of streaming applications such as multimedia by avoiding redundant computations. In associative memory, a set of frequent patterns that represent basic functions are pre-stored in ternary content addressable memory (TCAM) and reused. The primary limitation to using associative memory in modern parallel processors is the large search energy required by TCAMs. In TCAMs, all match rows, except hit rows, precharge and discharge in every search operation, resulting in high and undesirable energy consumption. In this paper, we propose a new multiple-access single-charge (MASC) TCAM architecture which is capable of searching TCAM contents multiple times with a single precharging cycle. In contrast to previous designs, the MASC TCAM keeps the match-line voltage of all miss-rows high and uses their charge for the next search operation, while only the hit rows discharge. We use a periodic refresh scheme to guarantee the accuracy of the search. We also implement a new type of approximate associative memory by setting longer refresh times for MASC TCAMs, which yields search results within 1–2 bit Hamming distances of the exact result. Our evaluation on AMD Southern Island GPU shows that using MASC associative memory can improve the average GPGPU energy efficiency by 36.6%, 40.2% and 39.4% for exact matching, selective 1-HD and 2-HD approximations respectively, with acceptable quality of service (PSNR>30dB). These energy savings are 1.8X and 1.6X higher than GPGPU using exact matching TCAM and approximation TCAM that uses voltage overscaling, respectively.

Ternary content addressable memory (TCAM) is used for high-speed table lookups. The dynamic power consumption of TCAMs is one of the main challenges for keeping up with high performance requirements. System level reliability is impacted by devices that produces large peak current demands on the power grid. This paper presents a TCAM compiler based on a static complementary TCAM bitcell for reduced dynamic power and reduced decoupling capacitance(dcap) requirement. The two stage architecture comprise of static TCAM cells with a match forward feature and then a static AND-tree structure. This TCAM compiler configurations have been implemented on 40nm CMOS technology testchip and experimental results demonstrate the performance upto 650Mhz and 0.5fJ/bit/search energy for a 512wordsx256bit macro.

Accurate traffic and latency measurements are the foundation of many network management tasks, including traffic engineering and network provision, network diagnosis and fault recovery. However, SNMP-based traffic measurement techniques in traditional IP networks only provide measurements for link loads, which cannot lead to accurate measurements. For link latency measurement, it has been shown that a traditional IP network needs to deploy a large number of monitors to achieve accurate measurements. The software-defined network (SDN) architecture opens up new opportunities to tackle the traffic matrix estimation and latency measurement problems. For the traffic estimation problem, the counter in a flow table entry of an SDN switch can directly measure the size of a matched flow. This dramatically increases the number and type of flows that can be measured accurately. For link latency measurement, SDN switches provide flexible routing and hence allow even non-shortest paths to be measured in the network. This routing flexibility can reduce the number of monitors deployed in the network to achieve a complete measurement of all the link latencies. But the additional measurement capabilities of SDNs also have limitations: the flow table entries added for measurements must be limited due to the high cost of ternary content-addressable memory (TCAM), and the amount of additional traffic for measurement should also be confined. Under these constraints, this research investigates the traffic matrix estimation and link latency measurement problems for a pure SDN network and a hybrid SDN network. A hybrid network, which consists of SDN switches and conventional routers, will exist for some time to come since it is economically impossible to replace every conventional router overnight. For the traffic matrix estimation problem, we propose a new estimation framework, which can be used in both SDNs and hybrid SDNs. Performance evaluation results show that the new framework can achieve highly accurate traffic measurement with a small number of TCAM entries. For the link latency measurement problem, we first present minimum monitor placement schemes in hybrid SDNs. It has been shown that our schemes not only reduce the number of required monitors but also guarantee full link measurements even when link weights change. We then present two time-stamp-based link latency measurement schemes for pure SDNs and show that the proposed schemes can minimize the number of consumed TCAM entries and the amount of traffic generated for measurement.

Ternary content addressable memories (TCAMs) are becoming very popular due to the simple-to-design IP lookup units included in high-speed routers; they are fast and simple to manage, and they provide a one-clock lookup solution. However, a major drawback of TCAM-based IP lookup schemes lies in their high power consumption. Thus, the rapid increase of routing tables inevitably deteriorates TCAM power efficiency. Although on-chip TCAM minimizers aim for the TCAM power efficiency in a fast time and at a small memory amount, the minimizers are not efficient in a large scale prefix table. In this paper, we present a hash-based on-chip TCAM minimization for a power-and throughput-efficient IP lookup. In a hash-based TCAM minimization (HTM), we convert prefixes into keys and merge keys with a fast hash lookup in an O(nW) complexity, where n is the number of prefixes and W is the number of IP bits. Additionally, by building a forest of merging trees and choosing a subset among them, we can achieve a higher minimization ratio. The simulation with two routing tables shows that our HPM scheme uses 8.6 and 4.0 times fewer computation time and memory, compared to a contemporary on-chip minimizer.