Efficient Temporal Arithmetic Logic Design for Superconducting RSFQ Logic

Over the last decades, designing reversible arithmetic circuits is one of the interesting research areas because of its ability to reduce power consumption in the circuits. This paper proposes two new design approaches of reversible binary-coded decimal (BCD) multiplier. The realization of such BCD multiplier has been achieved through binary multipliers, multiplexers, and a binary-to-BCD converter. Four types of multiplications, viz. [Formula: see text], [Formula: see text], [Formula: see text], and [Formula: see text] multiplications, have been utilized for such binary multiplication and are implemented parallelly as a combined multiplier to reduce ancilla inputs (AIs) and garbage outputs (GOs). We also propose a novel reversible BCD adder for a reversible binary-to-BCD converter with reducing AIs and GOs. The first design of the reversible BCD multiplier is integrated with the proposed BCD adder in the binary-to-BCD converter. Furthermore, the proposed reversible BCD adder is modified to reduce the AIs and the GOs, which is then integrated into the second design of the reversible BCD multiplier. The results offer appreciable reductions of AIs and GOs by at least [Formula: see text]16% and [Formula: see text]43%, respectively, compared to the existing designs found in the literature.

Computation intensive applications such as DSP, image processing, floating point processors and communication technologies today require efficient binary multiplication which usually is the most power and time consuming block. This paper proposes an efficient design for unsigned binary multiplication to reduce delay. A 16×16-bit multiplier has been designed which is based on Vedic Karatsuba algorithm. It is optimized using adaptive and recursive approach combined with square-root-carry-select-adder. The designs have been coded in Verilog, synthesized in Cadence Genus and physically verified with Cadence Innovus in GDSII under ASIC platform.

Low power, high speed approximate multiplier for error resilient applications

SummaryAccurate prediction of the solubility of chemical substances in solvents remains a challenge. The sparsity of high-quality solubility data is recognized as the biggest hurdle in the development of robust data-driven methods for practical use. Nonetheless, the effects of the quality and quantity of data on aqueous solubility predictions have not yet been scrutinized. In this study, the roles of the size and the quality of data sets on the performances of the solubility prediction models are unraveled, and the concepts of actual and observed performances are introduced. In an effort to curtail the gap between actual and observed performances, a quality-oriented data selection method, which evaluates the quality of data and extracts the most accurate part of it through statistical validation, is designed. Applying this method on the largest publicly available solubility database and using a consensus machine learning approach, a top-performing solubility prediction model is achieved.

With advent of digital circuits and systems, multipliers have become important functional blocks in digital and mixed-mode operations, in fast processors and micro-controllers design for applications in signal processing, data converters etc. Unfortunately however, very few original algorithms have been reported till date for speed-power optimization in multiplier design. As such processors and/ or digital systems having multiplier blocks continue to use the age-old time-tested Booth algorithm combined with its modifications proposed by Wallace and Dadda. Hence it became imperative to explore new fast multiplier algorithms and optimize their architectures in order to minimize area, complexity by reducing multiplication steps, to maximize speed, yet limiting power-dissipation. This paper re-introduces the Vedic algorithm named Karatsuba-algorithm that was invented for decimal-multiplication and then proposes a novel technique to make it a multi-level, recursive algorithm to further maximize the speed advantage in binary multiplication. A performance comparison of existing array algorithms like Booth Structure and Wallace Tree with the proposed Karatsuba technique and its recursive multi-tiring proposed by these authors, reveal that the proposed modification on Karatsuba algorithm results in most optimized performance on speed-power.

Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell

Field-programmable gate arrays (FPGAs) can efficiently implement custom applications via their embedded digital signal processor (DSP) slices, including binary multipliers. An increasing number of binary multipliers belonging to a DSP slice usually demonstrate that it has the capacity to process as many multiplication operations as possible in one clock cycle. In order to fully utilize the DSP resource, in this paper, we propose a novel DSP slice optimization method to achieve parallel multiplication on single DSP slice, namely PMSDS. First, the PMSDS splits multiplicators into two separate parts, i.e., valid bits and vacant bits, using a customized polynomial algebra method. Then, the PMSDS pre-calculates the maximum number of overflow bits combining the above-mentioned polynomial algebra method. Finally, it computes the total multiplicators' bit numbers and parallel the final multiplicators. We also propose an optimization model to find the best parallel solution according to the performance and precision of a single DSP slice. Moreover, we implement a PMSDS-based matrix multiplication algorithm supporting the computing precision dynamically changing. The experiments based on a large-scale and real-world matrix multiplication show that the PMSDS has better performance in latency and resource utilization than the traditional, add-tree, and full-unroll methods and is more outstanding in frequency and dynamic power consumption comparing with the state-of-the-art methods.

Today FPGAs are used in many digital signal processing applications. In order to design high-performance area efficient DSP pipelines various arithmetic functions and algorithms must be used. In this work, FPGA-based functional units for Cosine, Arctangent, and the Square Root functions are designed using bipartite tables and iterative algorithms. The bipartite tabular approach was four to 12 times faster than the iterative approach but requires 8-40 times more FPGA hardware resources to implement these functions. Next, these functions along with the FPGA hardware multipliers and a reciprocal bipartite table unit are used for hardware rectangular-to-polar and polar-to-rectangular conversion macro-functions. These macro-functions allow for a 7-10 times performance improvement for the high-performance pipelines or an area reduction of 9-17 times for the low cost implementations. In addition, software tool to design FPGA based DSP pipelines using the Cosine, Sine, Arctangent, Square Root, and Reciprocal units with the hardware multipliers is presented.

A radix-10 multiplication is the foremost frequent operations employed by several monetary business and user-oriented applications, decimal multiplier using in state of art digital systems are significantly good but can be upgraded with time delay and area optimization. This work is proposed a more area and time delay optimized new design of overloaded decimal digit set (ODDS) architecture-based radix-10 multiplier for signed numbers. Binary coded decimal (BCD) to binary followed by binary multiplication and finally binary to BCD conversion are 3 major modules employed in radix-10 multiplication. This paperwork presents a replacement technique for binary coded decimal (BCD) to binary and vice-versa convertors in radix-10 multiplication. A novel addition tree structure called as partial shifter adder (PSA) tree-based approach has been developed for BCD to binary conversion, and it is used to add partially generated products. To meet our major concern i.e. speed, we need particular high-speed multiplication, hence the proposed PSA based radix-10 multiplier is using vertical cross binary multiplication and concurrent shifter-based addition method. The design has been tested on 45nm technology-based Zynq-7 field programmable gate array (FPGA) devices with a 6-input lookup table (LUTs). A combinational implementation maps quite well into the slice structure of the Xilinx Zynq-7 families field programmable gate array. The synthesis results for a Zynq-7 device indicate that our design outperforms in terms of the area and time delay.

<p>Thesis examined at the University of Nottingham in April 2018, accepted in May 2018. </p>

Research on the immune system and cancer has led to the development of new medicines that enable the former to attack cancer cells. Drugs that specifically target and destroy cancer cells are on the horizon; there are also drugs that use specific signals to stop cancer cells multiplying. Machine learning algorithms can significantly support and increase the rate of research on complicated diseases to help find new remedies. One area of medical study that could greatly benefit from machine learning algorithms is the exploration of cancer genomes and the discovery of the best treatment protocols for different subtypes of the disease. However, developing a new drug is time-consuming, complicated, dangerous, and costly. Traditional drug production can take up to 15 years, costing over USD 1 billion. Therefore, computer-aided drug design (CADD) has emerged as a powerful and promising technology to develop quicker, cheaper, and more efficient designs. Many new technologies and methods have been introduced to enhance drug development productivity and analytical methodologies, and they have become a crucial part of many drug discovery programs; many scanning programs, for example, use ligand screening and structural virtual screening techniques from hit detection to optimization. In this review, we examined various types of computational methods focusing on anticancer drugs. Machine-based learning in basic and translational cancer research that could reach new levels of personalized medicine marked by speedy and advanced data analysis is still beyond reach. Ending cancer as we know it means ensuring that every patient has access to safe and effective therapies. Recent developments in computational drug discovery technologies have had a large and remarkable impact on the design of anticancer drugs and have also yielded useful insights into the field of cancer therapy. With an emphasis on anticancer medications, we covered the various components of computer-aided drug development in this paper. Transcriptomics, toxicogenomics, functional genomics, and biological networks are only a few examples of the bioinformatics techniques used to forecast anticancer medications and treatment combinations based on multi-omics data. We believe that a general review of the databases that are now available and the computational techniques used today will be beneficial for the creation of new cancer treatment approaches.

The authentication via accelerometer-based biometric gait recognition offers a user-friendly alternative to common authentication methods on smartphones. It has the great advantage that the authentication can be performed without user interaction. When the user is walking, his walk-pattern can be extracted from the accelerations measured using the integrated sensors of the smartphone. This pattern can be used for authentication. A study showed that users often deactivate the authentication methods of their mobile devices because they consume too much time. Because all steps necessary to perform biometric gait recognition can be executed in the background, no user interaction is necessary for the presented technique. Performing a continuous authentication while the user is walking, an up-to-date authentication result is available at any point in time. During log-in, no calculations are necessary anymore, hence there is no delay. Only in cases where the user is not walking, an alternative authentication method has to be used. This is a great benefit for the user because he has the advantages of a phone which is protected by authentication but without the disadvantages common methods impose. This high user-friendliness is likely to increase the number of smartphones for which the screen-lock is linked with an authentication. Therefore, a higher security of the data stored in smartphones can be achieved. A misuse of the stored information by an unauthorized user can be prevented. Due to the growing distribution of powerful smartphones, the number of available applications is increasing as well. These applications result in a growing amount of data stored on the devices, which make the protection of the device necessary. These data comprise e.g. addresses, appointments or GPS-information. Additionally, some applications, e.g. of e-mail-providers or social networks, require the user to authenticate himself. Often these credentials are stored by the user on the phone, such that it is not necessary to enter them each time. In case an unauthorized person has access to such a phone he can use these services without restrictions and therefore substantially harm the user. The objective of this thesis was to develop methods for accelerometer-based biometric gait recognition which achieve sufficient low error rates, as well as to demonstrate that their computational effort is low and allows for an execution on current smartphones. Because the basis of existing methods is the extraction of gait cycles (i.e. two steps) from the accelerometer data, a cycle-based method was developed and evaluated in a scenario test. This method uses raw data of the gait cycles as feature vectors and accomplishes the classification using distance functions. In addition, a further approach was selected, which does not need the time-costly and error-prone gait cycle extraction. Instead, it is using overlapping segments of a fixed time length. Several features are extracted from these segments and combined to feature vectors. Machine learning algorithms are used for classification. A benchmark of the approaches on a challenging database showed that these methods yield low equal error rates between 6% and 7% and are outperforming the cycle-based methods. These error rates were achieved under the realistic conditions that training and probe data are not collected on the same day. It was shown that five minutes of gait data are sufficient to thoroughly train the models. It should be regarded that the training data contain the different walking velocities at which the user should be recognized later on. To obtain low false rejection rates, the classification should be based on around three minutes walk data. Two of the developed methods were implemented on a smartphone. It was shown that both methods are able to perform the classification fast enough to allow for an authentication without delay for the user.

This paper proposes a control technique for DC motors which can determine the time response of speed, under both no load and on load conditions, in less than 2 seconds. It is operated by an 8-bit binary rate multiplier (BRM) under the PI control process. The motor under test is a two-quadrant type. The BRM 8-bit are generated from 8 principle waveforms by linear combination; finally 256 waves are attained. These waveforms are sent to control the motor with the required speed. It is known that BRM give low ripple-less than 1%-and, hence, less noise disturbance to the system. These BRM can be applied to reverse motor direction with fast response or sudden stop. Energy fed to the motor is also low but gives high efficiency.

This paper provides an efficient Montgomery modular multiplication technique, such as high-performance Montgomery modular multiplier, which is the most important arithmetic functional unit. The throughput of this multiplier is critical to the overall performance of these digital multiplication systems, which is measured in bits per second. The suggested work in this study proposes a Montgomery modular multiplier architecture that incorporates a unique adaptive hold logic (AHL) circuit to achieve a high level of performance. Because by the variable latency, the multiplier can deliver increased throughput while also adjusting the AHL circuit to prevent performance decline caused by the aging aware effect. Therefore, this proposed multiplier was developed using Verilog HDL and Synthesized in a Xilinx FPGA, which reduced the number of clock cycles required for operand pre-computation and conversion of format. As a result, high throughput can be achieved by hiding the additional clock cycles required for operand pre-computation and conversion of format. According to the experimental findings, our suggested design with 32-bit multipliers may provide up to a significant performance boost when compared to current 32-bit Montgomery Multipliers in terms of speed and efficiency.

This paper introduces a versatile and efficient design methodology for optimizing wide-angle impedance matching (WAIM) configurations, enhancing the scanning range of arbitrary antenna arrays. The three-layered structure is modeled using the generalized scattering matrices (GSMs) of the layers, incorporating sufficient excited modes for efficient input impedance calculation. To broaden the method’s applicability and meet manufacturing requirements, it also considers dielectric materials other than air between the array and WAIM. Machine learning (ML) algorithms are integrated to evaluate WAIM characteristics, reducing calculation time and resources while enhancing adaptability to new structures with minimal designer intervention. Decision Tree-based models are chosen to provide accurate prediction while minimizing the dataset preparation time. The methodology involves training a network using three ML algorithms, including decision tree, bagging, and random forest. Optimal WAIM parameters are efficiently determined using a genetic algorithm (GA). Three matching layers are designed and validated for several arrays operating at the frequency range between 9 and 11 GHz. The random forest model shows the best performance in predicting the WAIM behavior, with RMSE, scores, MAPE of 0.033, 0.916, and 2.161, respectively. Results demonstrate that the designed WAIMs effectively enhance the scanning range of both microstrip and waveguide arrays within the desired frequency range. The method achieves a calculation time of 0.3 s per angle, significantly faster than previous approaches, with a total runtime under an hour and minimal RAM usage (9.7 MB). This method offers an efficient framework for developing tools to design wide-angle scanning arrays and expand their applications.