Efficient Wait-Free Linearizable Implementations of Approximate Bounded Counters Using Read-Write Registers

A method is given for constructing a max register, a linearizable, wait-free concurrent data structure that supports a write operation and a read operation that returns the largest value previously written. For fixed m, an m-valued max register can be constructed from one-bit multi-writer multi-reader registers at a cost of at most [lg m] atomic register operations per write or read. The construction takes the form of a binary search tree: applying classic techniques for building unbalanced search trees gives an unbounded max register with cost O(min(log v, n)) to read or write a value v, where n is the number of processes.It is also shown how a max register can be used to transform any monotone circuit into a wait-free concurrent data structure that provides write operations setting the inputs to the circuit and a read operation that returns the value of the circuit on the largest input values previously supplied. The cost of a write is bounded by O(Sd min([lg m], n), where m is the size of the alphabet for the circuit, S is the number of gates whose value changes as the result of the write, and d is the number of inputs to each gate; the cost of a read is min([lg m], O(n)). While the resulting data structure is not linearizable in general, it satisfies a weaker but natural consistency condition. As an application, we obtain a simple, linearizable, wait-free counter implementation with a cost of O(min(log n log v, n)) to perform an increment and O(min(log v, n)) to perform a read, where v is the current value of the counter. For polynomially-many increments, this becomes O(log2n), an exponential improvement on the best previously known upper bounds of O(n) for an exact counting and O(n4/5+e) for approximate counting.Finally, it is shown that the upper bounds are almost optimal. We prove that min([lg m], n − 1) is a lower bound on the worst-case complexity for any solo-terminating deterministic implementation of an m-valued bounded max register, which is exactly equal to the upper bound for m ≤ 2n−1. The same bound also holds m-valued counters. Furthermore, even in a solo-terminating randomized implementation of an n-valued max register with an oblivious adversary and global coins, there exist simple schedules containing n − 1 partial write operations and one read operation in which, with high probability, the worst-case step complexity of a read operation is Ω(log n log log n) if the write operations have polylogarithmic step complexity.

We consider a set of users wishing to receive a service in an asynchronous distributed system. Such users declare their wishes and then wait to gain admittance to be served. Except for the initial transient period, at least one user must be waiting to be served, and the system should be as fair as possible for users. A procedure that ensures such a situation is called a turn function. It can be easily implemented in the asynchronous multi-writer/reader shared memory model. The turn function is useful to solve some problems concerning temporal orders within an asynchronous distributed system (e.g., the mutual exclusion problem and the k-exclusion problem). In this paper we propose an algorithm for the turn function that can be implemented in the single-writer/multi-reader shared memory model. Its implementation is simpler than the general method of simulating operations of multi-writer/reader shared variables by using a bounded concurrent time-stamp scheme in the single-writer/multi-reader shared memory model. We show the correctness of our algorithm and discuss its efficiency.KeywordsShared VariableService RegionMutual ExclusionRead OperationRelease RelationshipThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

: One of the most difficult issues that must be addressed when studying a class of parallel algorithms is the problem of choosing a model that captures the inherent difficulty of implementing these algorithms on a multiprocessor architecture. Shared memory models have proven to be an effective tool for deriving lower bounds on the complexity of comparison problems. In particular, a speed-up of lg(P) is possible for the problem of finding an element in an N-element sorted list, and speed-ups of PlglgP and P are possible for merging N-element sorted lists of P processors for the cases N=P and PN respectively. In practice, these speed-ups are not attainable since the shared memory models ignore many practical considerations in multiprocessor systems, such as interprocessor communications, distribution of data on local memories and limited fan-out of memory locations. In this paper we introduce a model for parallel computation that is strictly weaker than the shared memory models. The model is based on an actual machine currently being constructed (ZMOB). We examine the communication facilities available in the model and show that lower bounds for merging and searching on shared memory models are attainable (within a constant).

This paper proposes security constrained economic power dispatch (SCED) of the generators using parallel artificial bee colony (PABC) algorithm for electricity markets. The proposed non-linear optimization problem considers simultaneous minimization of deviations from scheduled transactions and minimization of fuel cost of the generators. The problem is formulated as a constrained optimization problem in a way that insures a secure-economic system operation. Incorporation of economic load dispatch (ELD) with voltages and lineflow constraints significantly relieves the assumptions imposed on the optimized objective function. The proposed approach has been tested on two representative systems, i.e. IEEE 14 bus and IEEE 30 bus systems respectively. Here, the message passing interface based technique is used in the PABC algorithm in a shared memory model. The time complexity and the solution quality with respect to the number of processors in a cluster are thoroughly analyzed.

The paper proposes a surprisingly simple characterization of task computability of the wait-free shared-memory model in which processes, in addition to read-write registers, have access to k-test-and-set objects. Our characterization is expressed in the form of an affine task: a subcomplex of some iteration of the standard chromatic subdivision. This appears to be the first topological characterization of a model in which processes communicate via long-lived objects beyond read-write registers.

Microtasking versus Message Passing Parallelisation of the 3D-Combustion Code AIOLOS on the NEC SX-4

Distributed shared memory (DSM) systems allow programmers to use a shared memory programming model on distributed systems. However, DSM systems present new challenges to performance evaluation and debugging. While programmers write programs with a shared memory model using shared variables and shared memory synchronization primitives to coordinate processes, most performance problems arise from the implementation of these abstractions with messages. Because the DSM abstraction hides the underlying message passing, it is difficult to identify the sources of performance problems. We have developed an instrumentation system and performance evaluation techniques for DSM systems that correlate message passing behavior in the lower levels of a DSM system with the higher-level shared memory programming abstractions. We have developed a prototype tool called Xunify to demonstrate the feasibility of such an approach. Xunify provides graphical animations of DSM programs at three distinct levels and offers a powerful event filtering facility capable to help show system behavior corresponding to specific DSM constructs.

OpenMP is an architecture-independent language for programming in the shared memory model. OpenMP is designed to be simple and powerful in terms of programming abstractions. Unfortunately, the architecture-independent abstractions sometimes come with the price of low parallel performance. This is especially true for applications with an unstructured data access pattern running on distributed shared memory systems (DSM). Here, proper data distribution and algorithmic optimizations play a vital role for performance. In this article, we have investigated ways of improving the performance of an industrial class conjugate gradient (CG) solver, implemented in OpenMP running on two types of shared memory systems. We have evaluated bandwidth minimization, graph partitioning and reformulations of the original algorithm reducing global barriers. By a detailed analysis of barrier time and memory system performance, we found that bandwidth minimization is the most important optimization reducing both L2 misses and remote memory accesses. On a uniform memory system, we get perfect scaling. On a NUMA system, the performance is significantly improved with the algorithmic optimizations leaving the system dependent global reduction operations as a bottleneck.

In this paper, we propos a new shared memory model: Transactionalmemory Coherence and Consistency (TCC).TCC providesa model in which atomic transactions are always the basicunit of parallel work, communication, memory coherence, andmemory reference consistency.TCC greatly simplifies parallelsoftware by eliminating the need for synchronization using conventionallocks and semaphores, along with their complexities.TCC hardware must combine all writes from each transaction regionin a program into a single packet and broadcast this packetto the permanent shared memory state atomically as a large block.This simplifies the coherence hardware because it reduces theneed for small, low-latency messages and completely eliminatesthe need for conventional snoopy cache coherence protocols, asmultiple speculatively written versions of a cache line may safelycoexist within the system.Meanwhile, automatic, hardware-controlledrollback of speculative transactions resolves any correctnessviolations that may occur when several processors attemptto read and write the same data simultaneously.The cost of thissimplified scheme is higher interprocessor bandwidth.To explore the costs and benefits of TCC, we study the characterisitcsof an optimal transaction-based memory system, and examinehow different design parameters could affect the performanceof real systems.Across a spectrum of applications, the TCC modelitself did not limit available parallelism.Most applications areeasily divided into transactions requiring only small write buffers,on the order of 4-8 KB.The broadcast requirements of TCCare high, but are well within the capabilities of CMPs and small-scaleSMPs with high-speed interconnects.

Long-lived and adaptive implementations of mutual exclusion and renaming in the read/write shared memory model are presented. An implementation of a task is adaptive if the step complexity of any o...

M-PVM is an implementation of PVM designed to work efficiently in parallel architectures supporting multithreading and the shared memory model. In particular, the current M-PVM implementation is running within MULPLIX, a Unix-like operating system designed to efficiently support parallel applications running on MUL TIPLUS, a distributed shared memory parallel computer under development at the Federal University of Rio de Janeiro. M-PVM is a parallel programming library built on top of the MULPLIX parallel programming primitives. Within M-PVM, PVM tasks are mapped onto MULPLIX threads. Two approaches have been adopted for the implementation ofthe message passing primitives. In the first approach a single copy of the message in memory is shared by all destination M-PVM tasks. The second approach replicates the message for every destination task but requires less synchronization. MPVM is not totally compatible with standard PVM but offers an environment which simplifies the portability of PVM applications to multithreaded shared memory platforms, in most cases, with performance improvements. Experimental results comparing the performance of M-PVM and PVM applications running on a 4-processor Sparcstation 20 under Solaris 2.5 are presented. These results show that M-PVM can produce speed-up gains in the range of 5 to 10% in relation to PVM.

A variety of models have been proposed for the study of synchronous parallel computation. We review these models and study further some prototype problems. We distinguish two classes of models, fixed connection networks and models based on a shared memory. Routing is the prototype problem for the networks. In particular, routing provides the basis for simulating the more powerful shared memory models. We show that a simple but important class of deterministic strategies (oblivious routing) is necessarily inefficient with respect to worst case analysis. Routing can be viewed as a special case of sorting and the existence of a deterministic O(logn) routing or sorting algorithm for an n processor fixed connection network remains open. However, if we consider the more powerful class of shared memory models, we are -&-ldquo;almost-&-rdquo; able to achieve such an efficient sort via Valiant's parallel merging algorithm. Within a spectrum of models, we show that log log n - log log r is asymptotically optimal for rn processors to merge two sorted lists of n elements.

The performance of computational devices is steadily increasing. Recently, the main contributor to the increasing performance has been an increasing number of cores rather than increased performance for individual cores. This trend is not only visible in high-end de-vices, such as powerful workstations, but also in low-end devices such as smartphones and many embedded devices. Due to this trend, and to the ubiquity of multicore systems, it is increasingly important for computer science students to have at least some familiarity with working with concurrent programs, as they are likely to encounter such programs in some shape or form in their future professional careers. In this thesis, we use the term concurrent programming to emphasize the focus on concurrency in a programming context, as opposed to concurrency in isolation. Prior work has shown that students struggle with learning concurrent programming. This is not surprising in and of itself, as concurrency is generally considered to be a difficult topic. To help students learn concurrent programming, it is important to consider why they find the topic difficult. As such, the first part of this thesis aims to gain better insights into these difficulties. This is done partly by studying prior work in the literature and partly by conducting new research. The results show that the struggles are not only due to the difficulty involved in understanding the new concepts related to concurrency. Rather, a large portion of students’ struggles can be attributed to the fact that the non-determinism in concurrent programs requires a more formal approach to programming. The transition from an informal approach, where students are able to rely on ad-hoc testing, to a more formal approach is difficult in and of itself, but it also highlights problems in students’ understanding of fundamental programming skills. For example, without a detailed enough understanding of scope, aliasing and references it is difficult to reason about what data is shared between threads. In light of these results, the remainder of this thesis describes ways of helping students learn concurrent programming. This is achieved by developing a program visualization tool, called Progvis, which is capable of visualizing the behavior of concurrent programs written in the C language. Progvis is unique in the sense that it focuses not only on concurrency, but also illustrates how concurrency interacts with the fundamental concepts that were found to be problematic. As such, it is able to give students a complete and accurate picture of the visualized program’s behavior. To further help students, Progvis also includes a model-checker that can automatically find concurrency issues, thereby helping students to easily see whether their reasoning about the program’s behavior was correct or not. The results suggest that the visualizations generated by Progvis have the potential to help students learn concurrent programming. A small pilot study showed that students who used Progvis were able to solve concurrency problems faster and arrived at better solutions compared to students who only used traditional tools. To evaluate long-term effects on learning, Progvis was also integrated into a course on concurrency and operating systems. Comparing the students’ performance on the final exam showed that the students who had used Progvis were more likely to correctly associate their synchronization with the associated data compared to students who had not used Progvis during the course. Even though no significant increase was observed in students’ overall performance, these results suggest that using Progvis does indeed have a positive impact on students’ learning.

This paper addresses the problem of the 3D game design aided by multi-dimensional collision detection algorithm with GPU optimization. For the designed model, our task will be focused on the 3D game design, the GPU performance on the image computing and neural network computing will be essential, hence, the graph neural network algorithm is considered. This study firstly considers the GPU optimization with shared memory model. Shared memory can be used to design the memory access mode in order to realize the combination of the memory access which improves the efficiency. Then, this study considers the multi-dimensional collision detection algorithm design. In order to achieve the unique representation of matrix translation and also spatial points, this paper then adopts the homogeneous coordinate system in matrix transformation. That improves the traditional model. Furthermore, the 3D game design steps are clarified. Based on the experiment under different scenarios, the game design sample code, the GPU performance and algorithm performance are all tested.

SUMMARYOptical networks on chip based on silicon photonics have been proposed to reduce latency and power consumption in future chip multiprocessors. However, high performance chip multiprocessors use a shared memory model, which generates large numbers of short messages, creating high arbitration latency overhead for photonic switching networks. In this paper, we explore techniques that intelligently use information from the memory hierarchy to predict communication in order to setup photonic circuits with reduced or eliminated arbitration latency. Firstly, we present a switch scheduling algorithm, which arbitrates on a per memory transaction basis and holds open photonic circuits to exploit temporal locality. We show that this can reduce the average arbitration latency overhead by 60% and eliminate arbitration latency altogether for up to 70% of memory transactions. We then demonstrate that this switch scheduling algorithm operating with a central photonic crossbar or Clos switch has significant energy efficiency benefits over arbitration‐free photonic networks such as single writer multiple reader networks. Finally, we demonstrate that cache miss prediction can be used to predict 86% of more complex memory transactions involving multiple nodes or main memory. Copyright © 2014 John Wiley & Sons, Ltd.