Electrical design challenges in High Bandwidth Memory and Advanced Interface Bus interfaces on HD-FOWLP technology

As silicon scaling closer to physical limit, future reduction of the gate oxide does not lower down the cost per transistor. But the demand of higher functionality and lower cost of electronic devices do not slow down. Development of electronic devices metaphor to high-density package integration. What the electronic industries do is to break down a large die to a chiplet-based devices for improving yield and lower the total cost. Chiplet package become a key technology to continue Moore's law. With the intensive researches, multiple chiplet packages are evolved such as multi chips on Si interposer using TSV (2.5D), die to die stack on each other (3D), Fan-Out Multi Chip Module (FOMCM), and EMIB (Embedded Multi-Die Interconnect Bridge). These packages are developed for the server, high performance computing, router, and switcher markets. But, the integration of high bandwidth memory devices and multiple ASIC dies together requires very high I/O counts and signal transmitting. Thus, a much higher RDL (Redistribution Layer) layer counts, finer bump pitch and smaller line- space (L/S) are designed. Each of these chiplets has its limitations. Large 2.5D package has its cost concerns on large Si interposer and mismatch of the Si interposer with substrate on reliability test. Whereas, large FO-MCM technology is limited by finer L/S and higher layers count of RDL. Presently, the package is heading the bottleneck at 1/1 μm L/S, 5 layers RDL and 2 reticle size chip module. As for EMIB technology, it is constrained by L/S that could only down to 5/5 μm. In this paper, we have successfully developed a scalable chiplet package technology, namely Fan-Out Embedded Bridge (FOEB). This chiplet package enables near monolithic short reach BEOL connections between dies. FOEB can have multiple RDL layers and Si bridge that has much finer L/S for interconnection. In addition to, multiple dies can be bridged together into one single chip module. In this paper, the demonstration of FOEB test vehicle, which integrate chips by 1 ASIC die and 4 memory dies (1+4) with 4 embedded bridge dies on mold-based interposer, 3 layers of RDL are presented. By comparing packages using FOMCM and 2.5D to fabricate. FOEB package has much lower warpage and 2× lower stress value as compare to 2.5D. But similar to FOMCM. Owing to this reason, the FOEB chiplet package were tested 2x longer temperature cycle with condition-G without single failure as compared to 2.5D. The assembly yield of FOEB is comparable to FOMCM. And much higher than that of EMIB. Assembly of FOEB chiplet package adopts organic interposer. The wafer warpage changes from concave to convex shape after die attachment on the molded interposer. This limits some of the machines handling and induces wafer cracking. By properly select the right molding compound, and glass carrier CTE, we have successfully developed this FOEB chiplet and validated through reliability test. This chiplet allows us to scale the package to much higher I/O density, finer L/S, higher RDL layers, and number of dies that can be integrated into one single chip module.

Spurred by the industrial demands for terabyte/s bandwidth graphics module, high bandwidth memory (HBM) has been emerged to overcome the limitations of conventional DRAMs. Additionally, due to the fine pitch and high density interconnect routing between GPU and 4 HBMs in 2.5D terabyte/s bandwidth graphics module, HBM interposer has also been to the force. However, several signal integrity issues of the HBM interposer occur due to the manufacturing process constraints. In this paper, we design the HBM interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module. And then, in the designed HBM interposer, electrical performance of the HBM interposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain. With the simulation results, it is observed that the designed HBM interposer shows good signal integrity.

Based on High Bandwidth Memory (HBM) structure and taking into consideration the direct interconnection between the micro-bump and the end of the Cu-filled TSV, there is an interaction between the micro-bump joint and the Cu protrusion. To clarify this issue, in this study two geometric finite element models (i.e., 4-hi stack HBM structure and 8-hi stack HBM structure) are constructed and used to characterize the von Mises stress, volume fraction of plastic deformation region of the Cu-filled TSV, height of Cu protrusion and fatigue life of micro-bump joints with taking into account the interaction between the micro-bump joint and Cu protrusion. The simulation results manifest that micro-bump joints in 4-hi stack HBM model suffer larger average stress than those in 8-hi stack HBM model, and the volume fraction of plastic deformation region of Cu-filled TSV in the former model is also higher than that in the latter one. Interestingly, the height of Cu protrusion becomes equal at upper and lower ends of Cu-filled TSVs in upper TSV layers of 8-hi stack HBM model. From fatigue property point of view, 8-hi stack HBM model is superior to 4-hi stack HBM model.

State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.

Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-\mu \mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-\mu \mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $\mu$ -bumps with $25-\mu \mathrm{m}$ size on a $45-\mu \mathrm{m}$ pitch in the logic and $25-\mu \mathrm{m}$ size on a $55-\mu \mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-\mu \mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to integrate multiple functionalities and cost.

In this paper, we firstly proposed and electrical and thermal co-analyzed a novel through mold plate (TMP) for thermal management of high bandwidth memory (HBM). Thermal issues are bottlenecks in the development of HBM and 2.5-D/3-D ICs. The proposed TMP can be one of the promising solutions for advanced thermal management. Thermal coupling from the graphic processing unit (GPU) is the dominant factor for HBM thermal issues. A new thermal path can be achieved by installing the TMP in the epoxy molding compound (EMC) between GPU and HBM to significantly prevent thermal coupling from the GPU. By using 3D electromagnetic and fluent simulation, we verified the proposed TMP based on co-analysis of signal integrity (SI) and thermal integrity (TI). SI analysis considering both TMP and operating temperature provided the thermal and electrical superiority of TMP. As a result, the results showed the improvement of thermal integrity and signal integrity of the HBM by not only reducing HBM junction temperature by 10.3 °C but also decreasing jitter by 4.54 % compared to a conventional HBM graphic module.

Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation

The tremendous growth in smartphones and tablets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of integrated circuit (IC) devices, resulting in the need for more advanced and sophisticated packaging techniques. In particular, the integration of the application processor (AP) and dedicated memory has become increasingly complex. Smartphones and tablets have become virtual streaming devices requiring low power, high bandwidth memory (HBM). For quality, high-speed video and multi-tasking applications, the memory interface to the AP must have superior signal integrity to minimize crosstalk and insertion/return losses. In addition, the thermal management of the processor must allow the maximum clock speed and duty cycle for high-performance applications. Finally, to conserve battery life for the mobility device, the power distribution to the processor must be as efficient as possible. This creates a significant challenge for the semiconductor packaging industry to meet these demanding requirements for smartphone and tablet products. This paper introduces a leading-edge high-density fan-out (HD-FO) semiconductor packaging technology that addresses the need for higher levels of integration and improved electrical and thermal performance for mobile applications. This new innovative technique, called Silicon Wafer Integrated Fan-out Technology (SWIFT™) packaging, leverages the fine feature size and thin-film circuit patterning capabilities of wafer-level packaging. In addition, thin-film dielectric photolithography and pattern plating provides a significant reduction in package z-height, which is critical for advanced mobile devices. By incorporating a redistribution layer (RDL)-first/chip-last process flow, there is also an opportunity for yield optimization and cycle-time reduction. This work compares the electrical and thermal modeling results between a conventional Package-on-Package (PoP) and HD-FO SWIFT devices. The results reveal a highly integrated PoP structure with exceptional electrical, mechanical, and thermal performance benefits – compared to conventional organic laminate-based technologies – to meet the growing need for high-performance mobile applications.

AI data centers rely on accelerators that integrate logic dies with multiple stacks of highbandwidth memory (HBM) via advanced packaging such as chiponwaferonsubstrate (CoWoS). Because these inputs are nonsubstitutable complements, a shortage at either HBM or packaging yields zero deployable compute. We argue that common singledimension contractsrevenue sharing or quantity flexibilityfail when bottlenecks switch across complements. We propose a ComplementLinked Option (CLO): a contingent right that reserves matched bands of HBM and packaging capacity, exercised only after demand and shocks are observed. We develop a compact assembletoorder model with Leontief structure (shipments equal the minimum of demand, HBM, and packaging), state two formal propositions showing the dominance of CLO over separate options, and calibrate Monte Carlo experiments with public, documented expansions: HBM3E volume ramps in 20242025 and CoWoS capacity roughly doubling in 2024 and again in 2025. Using these anchors, we find 812% expected profit improvement and higher fill rates for CLO over a nooption baseline; CLO also outperforms separate options when premiums are charged per node.

Currently, the IC industry has been steadily advancing towards 7 nm and 5 nm nodes with further reductions projected in the near future to progressively create large number of inputs and outputs (IOs) at finer pitch. Today the high-density interconnect (HDI) organic redistribution layer (RDL) can only achieve an IO density of about 40 IOs per mm per layer with line and space of 6 μm and microvia diameter of 20 μm at 50 μm pitch. However, to achieve further increases in IO density, RDL with 1 μm routing lines and spaces together with 1 to 2 μm diameter microvias are required. Such advances in the RDL technology are of great importance to accomplish IO densities of 500 IOs/mm/layer to enable high bandwidths of 500 Gb/s at low cost. In this paper we present the latest progress at the Packaging Research Center, Georgia Institute of Technology in the following 4 key areas.1. Fine line photolithography: Various methods that can achieve 1 μm critical dimension (CD) are discussed and recent results on 1 μm L/S using both dry film and liquid photoresists together with advanced lithographic tools are presented.2. Small microvia creation: Microvia is the most important barrier limiting the RDL to achieve high IO density and fine IO pitch. In this paper, microvia diameter scaling down to 2 μm along with the feasibility to achieve 1 μm and via pitch of 4 to 8 μm using both photo and picosecond pulsed UV laser will be presented.3. Low Dk and Low Df dielectric materials: Dielectric material layers are an important part of RDL. For achieving multi-functional high speed and/or low loss systems and modules, dielectric layers with low Dk and/or low Df materials are critical. The material requirements, availability and process challenges will be addressed in this paper.4. Process methodology: The semi-additive process (SAP) has been the process of record for RDL fabrication. In this paper, the conventional SAP and its modifications such as modified-SAP (m-SAP) and advanced SAP (a-SAP) together with alternative organic damascene process (ODP) along with back-end- of-line (BEOL) will be reviewed and compared.Finally, considerations for future trends are presented.

In this article, for the first time, we propose channel characteristic-based deep neural network (DNN) models for accurate eye-height (EH) and eye-width (EW) estimation of high bandwidth memory (HBM) silicon interposer channels. The proposed models preprocess the design parameters that are highly relevant to the characteristics of the HBM channels. By taking account of the contribution of each design parameter to the eye diagram, the proposed models can accurately estimate the EH and EW of the channels even with a limited number of datasets. For verification, the proposed DNN models were applied to the microstrip and stripline channels of an HBM silicon interposer. Only redistributed layer (RDL) was used to clearly see the effect of reflecting the channel characteristics of the proposed method. We compared the proposed DNN models with various regression methods and a conventional fully connected multilayer DNN model. As a result, the proposed DNN models reduced the EH and EW error rates by 22.7 and 43.9&#x0025; compared to the other regression methods. In addition, the proposed DNN models not only reduced the error rates by 22.0&#x2013;28.4&#x0025; but also reduced the computing cost by 8.0&#x2013;9.4&#x0025;, compared to the conventional DNN model. Moreover, we compared the proposed models with various DNN models having other preprocessing structures. By showing 26.7 and 28.8&#x0025; lower EH and EW error rates than the other DNN models, we validated that the proposed models properly consider the most dominant design factors in preprocessing.

In this paper, we firstly proposed a thermal transmission line (TTL) based embedded cooling structure for advanced thermal management of a next-generation high bandwidth memory (HBM) module. Thermal issues are critical to the development of HBM and 2.5D/3D ICs. The proposed TTL based embedded cooling structures can be one of the promising thermal management solutions for the 2.5D/3D ICs. The previous embedded cooling structures have thermal management limitations of the difficulties of cooling the internal heat of the 2.5D/3D ICs each layer. The proposed TTL transfers internal heat to the coolant to lowering junction temperature. Moreover, we checked the fabrication feasibility of the TTL with through silicon vias (TSVs). By using 3D electromagnetic (EM) and 3D fluent simulations, we analyzed the proposed TTL considering signal integrity (SI) and thermal integrity (TI). SI analysis showed the TTL does not contribute critical SI issues for HBM on-chip TSV channels. TI analysis provided the thermal management superiority of the TTL. As a result, it showed the improvement of TI of HBM module decreased HBM junction temperature by 4.789°C compared to the previous embedded cooling structure.

Heterogeneous integration is the key technology which is applied in HPC, AI and Could computing applications. Through the die to die interconnection, such as ASIC to HBM and ASIC to ASIC. the higher I/O density, wider data transimission bandwidth between memory to active die and lower RC delay are reuqired in chiplet integration. However, the heterogeneous integration between different funtional dies which lead varius process challenges, such as multilayered Redistribution Layers (RDL) warpage control, surface coplanarization treatment, and solder joint capability during the die bond (DB) process. Hence, in this paper, we demonstrate the large size FO-MCM (MultiChip Module) package with 6 layers RDL which sucessfully overcome the non-wetting issue and warpage effect by optimized RDL technology and compatible glass carrier selection during wafer process. In this study, we demonstrate Fan-out MCM (MultiChip-Module) with 6 layers RDL by 2/2 um line/space, meanwhile, the warapge effect has decreased 39% by particular glass which has the compatible CTE parameter and the thickness. Besides, in this experiment, we assess chip module warpage performance during reflow high temperature 250C of chip last FO-MCM, that is important for C4 bump non-wetting phenomenon when chip module bonding to substrate or directly SMT bonding to PCB. This multilayered RDL with the compatible glass technology bring a potential benefit to improve the TTV and warpage effect on RDL surface. The results of the reliability test including TCT 1000 cycle, u-HAST 192 hours and HTSL 1000 hours are qualified in this experiment. Undoubtedly, Heterogeneous integration with multi-layer Fan-Out RDL is the mainstream for the AI, Could computing and high bandwidth memory integration in the IC package industry, by utilizing this innovative Multi-layer RDL with the compatible glass technology, the stability and yield of the fine pitch die bond will be improved obviously.

Advanced non-volatile memory concepts such as the 1T1C ferroelectric (FE) random-access memory (FeRAM) and the 1T1C FE field-effect transistor (FeFET) can be realized by connecting a metal-ferroelectric-metal (MFM) capacitor placed in the back end of line (BEoL) of a microchip to the drain and gate contacts of a standard logic device, respectively. With the vertical distributed select devices in the front-end of line (FEoL) and the storage elements in the BEoL, both concepts increase the effective memory density of a microchip without introducing major changes in the FEoL fabrication technology. However, for advanced neuromorphic computing architectures, the 1T1C FeFET is the device of choice, since it provides non-destructive readout. The most promising material for the integration of FE non-volatile memory functionalities into the BEoL is Zr doped HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> (HZO). It crystallizes at low temperatures in the orthorhombic phase (the one with FE properties) and with a polycrystalline structure. The latter is important to enable analogue like switching in synaptic devices. Herein, the above-mentioned memory concepts are introduced and key steps to optimize the HZO films for the BEoL integration and for the neuromorphic computing use case are described.

High Bandwidth Memory (HBM) Dynamic Random Access Memory (DRAM) has emerged as a preferred choice for leading-edge graphics, networking and highperformance computing applications. HBM is also finding usage in artificial intelligence (AI), machine learning (ML) and other advanced applications that demand high bandwidth and high power efficiency. HBM systems are implemented in 2.5D technology in which the memory stack and System-on-Chip (SoC) are integrated using a silicon interposer in a single package. Unlike conventional Double Data Rate (DDR) systems, the memory channel in 2.5D HBM systems are not accessible outside the package, posing multiple challenges in post-silicon characterization, system validation and SoC bring up. This paper discusses the functional at-speed test challenges and solutions using IEEE1500 based test structures implemented in the PHY, complementing those in DRAM. The paper also discusses a novel method to allow channel pin access for receiver and transmitter characterization with minimal impact to normal operation. Silicon results are presented at different levels of system hierarchy that consists of Memory Controller (MC), Physical Layer (PHY) and DRAM. Together, these results demonstrate excellent test coverage of the complete HBM memory subsystem and efficient silicon debug support.