Electronic design automation in undergraduate digital system curriculum

Provision of free, downloadable industry-standard reconfigurable hardware EDA tools is a growing and welcome trend. Low cost, ever-more-complex FPGA-based embedded system development platforms with host interface control are becoming more readily available. This paper describes a series of structured VHDL workshop modules which use the Xilinx ISE Webpack/ModelsimXE electronic design automation (EDA) tools and Digilent Spartan-3 hardware development system. The described course implements an extendable embedded system, which performs a selection of image and audio processing applications, controlled by a host graphical user interface (GUI). A formal structured design, documentation and test methodology is incorporated throughout the course. Enhancements to EDA tool VHDL and diagram creation wizard support are proposed to aid VHDL capture automation and design visualisation. Improved student understanding and achievement level in VHDL programming, digital embedded system design techniques and FPGA implementation has resulted

In modern IC design, circuit designers often need to manually operate and move data among different EDA (Electronic Design Automation) tools. If these tools were installed in separate computers, due to the license and system requirements, the design flow will be frequently interrupted, to handle the dreary data movement work, and the design efficiency will thus be reduced. To alleviate the above problem, a seamless and efficient design flow would be a must. The aim of this paper is to propose a service-oriented integrated EDA environment that can improve the smoothness of the design flow and consequently increase the overall design productivity. In our approach, a multi-agent framework based on JADE platform is used to manage distributed EDA tools, which are encapsulated as agent services. Mobile agents are allowed to autonomously and concurrently migrate among computers to access services for IC designers. To facilitate that, a scripting language is designed for mobile agents to allocate tasks, cooperate with each other, and select appropriate services. To demonstrate the feasibility of our method, an Integrated Circuit Design Cycle Assistant System (ICDCAS) for simplifying the manual operations in IC design cycles is developed by combining two EDA tools: ModelSim and Xilinx ISE. The implemented system proves to have the features of time saving and being free of mistakes incurred by manually operating and configuring the sophisticated EDA tools.

Recent developments in EDA tools for power electronics modules have led to simultaneous analysis and optimization of package features with regard to electro-thermal and thermo-mechanical aspects. In this work, two of these EDA tools, PowerSynth and ParaPower, are linked together with a software application programming interface (API) to rapidly explore a combined electro-thermo-mechanical design space and present the user with co-optimized solutions and tradeoffs in a fraction of the time consumed using traditional analysis methods. An overview of this co-design process and its advantages over that of the traditional, iterative approach is presented along with an explanation of the methods used by the respective tools for analysis. Finally, additional considerations and constraints are introduced that ensure manufacturing feasibility and reliable operation at high voltages. A case study in co-design using these tools has been proposed for the final paper.

Advanced electronic design automation (EDA) tools, with their simulation, modeling, design rule checking, and optical proximity correction capabilities, have facilitated the improvement of first pass wafer yields. While the data produced by these tools may have been processed for optimal wafer manufacturing, it is possible for the same data to be far from ideal for photomask manufacturing, particularly at lithography and inspection stages, resulting in production delays and increased costs. The same EDA tools used to produce the data can be used to detect potential problems for photomask manufacturing in the data. A production implementation of automated photomask manufacturing rule checking (MRC) is presented and discussed for various photomask lithography and inspection lines. This paper will focus on identifying data which may cause production delays at the mask inspection stage. It will be shown how photomask MRC can be used to discover data related problems prior to inspection, separating jobs which are likely to have problems at inspection from those which are not. Photomask MRC can also be used to identify geometries requiring adjustment of inspection parameters for optimal inspection, and to assist with any special handling or change of routing requirements. With this foreknowledge, steps can be taken to avoid production delays that increase manufacturing costs. Finally, the data flow implemented for MRC can be used as a platform for other photomask data preparation tasks.

The incorporation of electronic design automation (EDA) tools in engineering curricula will better prepare graduates to enter the modern engineering marketplace. The engineering courses appropriate for EDA introduction are discussed, as are the tools themselves and their sources. Issues of computing platform, operating system, and tool suites are presented. Internet accessible public domain documents are provided to aid engineering schools in setting up a comprehensive EDA curriculum.

As the semiconductor industry moves into the next generation sub-nanometer design the quality of the electronic design automation (EDA) tools becomes more critical. With shrinking market windows and increasing time to market constraints the designers need reliable and robust EDA software tools to ensure that the design is manufacturable with an acceptable yield. This paper develops a balanced scorecard for implementing systemic quality in an EDA organization.

Over the course of 60 years, since the invention of the integrated circuit (IC), exponential improvements in cost, performance and power consumption were observed. Such advances have been strongly linked with the continuous reduction of the dimensions in manufactured ICs, but this trend has shown decreasing benefits as fundamental limits are reached. Notice that such tiny devices have increased variability, which generates unpredictable variations in the behavior of the manufactured devices. These uncertainties are typically addressed by defining margins on the clock period, estimated during the design phase. However, the overly conservative margins produce significant degradations in performance. Additionally, the evolution that enabled circuits with increasingly higher density of components, also resulted in an extremely complex IC design. At every step, electronic design automation (EDA) tools are challenged to handle this increasing complexity, requiring more powerful techniques to comply with the specification constraints within an affordable runtime. This thesis investigates alternatives in order to improve power, performance, area, and cost, using established IC manufacturing technologies. Advances in EDA are proposed in three distinct topics: area minimization using Boolean methods, area and delay reduction for designs based on fieldprogrammable gate array (FPGA), and an alternative clocking scheme to reduce timing margins. The first contribution consists of a technology-independent method for area minimization of combinational logic. Local optimization is applied on and-inverter graphs (AIGs), performing multi-output Boolean decomposition using two-literal divisors, targeting node count reduction. The second contribution regards two methods targeting technology mapping of FPGAs. On one hand, a functional decomposition approach, which uses the support size as cost function, exploring the inherent characteristics of FPGAs. On the other hand, an approach for recursive remapping, which reduces the structural bias of the subject graph, uses the mapping results as cost function, and obtains significant reductions in area and delay. The third contribution evaluates the dynamic variability mitigation and simplification of power delivery networks (PDNs) using an adaptive clocking scheme based on ring oscillator clocks (ROCs). The impact of the PDN parameters and ROC location is investigated, showing potential improvements in performance, leakage power and cost. A lo largo de los 60 años desde la invención del circuito integrado (CI), se han producido mejoras exponenciales en su coste, rendimiento y consumo de energía. Ese progreso esta fuertemente vinculado a la reducción continua de las dimensiones de fabricación de los circuitos integrados, pero esta tendencia ha ido mostrando menos beneficios a medida que se alcanzan límites fundamentales. Estos dispositivos minúsculos tienen una mayor variabilidad, lo que genera variaciones impredecibles en el comportamiento de los dispositivos fabricados. Estas incertidumbres generalmente se abordan mediante la definición de márgenes en el período de reloj, estimado durante la fase de diseño. Sin embargo, márgenes excesivamente conservadores producen degradaciones significativas en el rendimiento. Además, la evolución que permitió crear circuitos con una densidad de componentes cada vez mayor, también incrementado la complejidad de los CI. En cada paso del proceso de diseño, las herramientas de automatización de diseño electrónico (EDA) se enfrentan al desafío de manejar esta complejidad creciente, lo que requiere técnicas más potentes para cumplir con las restricciones impuestas por las especificaciónes dentro de un tiempo de ejecución asequible. Esta tesis investiga alternativas para mejorar el consumo de energía, el rendimiento, el área y el coste, utilizando las tecnologías de fabricación de CI ya establecidas. Los avances en EDA se proponen en tres temas distintos: minimización de área usando métodos booleanos, reducción de retardo y área para diseños basados en matrices de puertas programables (FPGA), y un esquema de reloj alternativo para reducir los márgenes de tiempo excesivamente conservadores. La primera contribución consiste en un método independiente de tecnología para minimizar el área de la lógica combinacional. Se aplica optimización local en grafos de AND-inversor, utilizando una descomposición Booleana de múltiples salidas con divisores de dos literales, con el objetivo de reducir la cantidad de nodos. La segunda contribución propone dos métodos para el mapeo tecnológico de los FPGA. Por un lado, un método de descomposición funcional, que utiliza el tamaño del soporte como función de coste, explorando las características inherentes de los FPGA. Por otro lado, un método de mapeo recursivo, que reduce la distorsión estructural del grafo sujeto, utiliza los resultados del mapeo como función de coste y obtiene reducciones significativas en área y retardo. La tercera contribución evalúa la mitigación de la variabilidad dinámica y la simplificación de la red de suministro de energía (PDN) utilizando un esquema de reloj adaptativo basado en un oscilador en anillo (ROC). Se investiga el impacto de los parámetros de la PDN y la ubicación del ROC, mostrando mejoras potenciales en el rendimiento, consumo estático y coste.

With Moore's law in effect, as the complexity of digital electronic circuits increases, the amount of time spent by the electronic design automation (EDA) tools to design such circuits also increases. It brings us to the point, where we need to improve the performance of EDA algorithms to fulfil the present and the future requirements of the EDA industry. Out of many algorithms used by these tools, Breadth First Traversal (BFT) is one of the most commonly used algorithms to traverse the gates of electronic circuits. In this paper, we present a new simple, fast and parallelizable BFT algorithm for sparse graphs, named H-BFT. We show that the CPU implementation of H-BFT is about 75× faster than the CPU implementation of the state of the art, the Sparse Matrix-Vector Product (SMVP) based BFT. Further, with the new features introduced by NVIDIA in their GPUs, we have accelerated both the state of the art SMVP based BFT implementation and our new H-BFT implementation. The best speedups we achieved via these accelerations are 180× and 25× for the SMVP-BFT and H-BFT respectively.

Electronic design automation (EDA) tools have facilitated the design of ever more complex integrated circuits each year. Synthetic biology would also benefit from the development of genetic design automation (GDA) tools. Existing GDA tools require biologists to design genetic circuits at the molecular level, roughly equivalent to designing electronic circuits at the layout level. Analysis of these circuits is also performed at this very low level. This paper presents the background and issues involved in the development of such a GDA tool for modeling, analysis, and design.

The rapid advancement of artificial intelligence (AI) has accelerated the semiconductor industry, driving chip performance requirements to unprecedented levels. However, conventional system-on-chip (SoC) designs are increasingly constrained by the physical and economic limits of monolithic scaling, where continued transistor miniaturization yields diminishing returns and rising fabrication costs. To address these challenges, the industry has shifted toward chiplet-based heterogeneous integration and advanced packaging technologies. By interconnecting multiple specialized chiplets through high-density, high-bandwidth interfaces, this modular approach improves scalability, reusability, and cost efficiency while enabling faster time-to-market. However, chiplet-based systems introduce significant design complexity, particularly in signal integrity (SI) and power integrity (PI), where highly constrained interconnects and power delivery networks must meet stringent electrical requirements. Traditional design methodologies rely heavily on expert-driven manual tuning and extensive full-wave electromagnetic simulations using electronic design automation (EDA) tools, resulting in long design cycles that can span weeks or months. To overcome these limitations, this thesis investigates the application of AI, particularly deep reinforcement learning (RL), to automate and optimize chiplet-based system design with a focus on SI and PI challenges in advanced packaging technologies. The research initially explores a supervised learning approach using convolutional neural networks (CNNs) to classify signal impairments from eye diagrams. While effective, this approach reveals a critical dependence on large labeled datasets, which are scarce in SI/PI domains, motivating a shift toward RL for autonomous design space exploration without labeled data. The first major contribution proposes an RL framework for automated power distribution network (PDN) design in a four-chiplet system. Two RL algorithms, Dueling Double Deep Q-Network (DDDQN) and Proximal Policy Optimization (PPO), are evaluated under different reward strategies. Results show that dense analytical rewards based on power domain squareness and bump proximity enable the RL agent to achieve lower self-impedance than human-designed PDNs, ensuring power integrity across 28 power domains. The complete PDN layout, which typically requires three months of manual effort, is generated in under one hour using a single GPU. The second contribution focuses on signal integrity optimization for chiplet interconnects in CoWoS redistribution layers (RDLs). An RL agent is trained using a reward function that balances eye width, voltage transfer function (VTF) crosstalk, and interconnect density. The agent explores design variations across data rates from 4 to 32 GT/s using a simulation environment integrated with commercial EDA tools. Experimental results demonstrate up to 24.67% improvement in eye width and over 22 dB reduction in VTF crosstalk while satisfying UCIe electrical specifications. The training process also generates labeled datasets for future supervised learning. The third contribution introduces an RL-based routing framework for UCIe bridge interconnects in advanced System-in-Package (SiP). Using Proximal Policy Optimization, the framework learns to generate routing layouts that comply with constraints such as ground-signal-ground structures, layer assignment, and congestion avoidance. It supports all UCIe module configurations and produces design rule check-compliant solutions within 100 training episodes, reducing design time from four weeks to less than one hour while improving signal distribution and reducing via usage. In summary, this thesis presents a unified AI-driven methodology for addressing SI and PI challenges in chiplet-based systems. The proposed RL frameworks significantly outperform traditional design approaches in both efficiency and quality, demonstrating the potential of deep RL to enable scalable and intelligent design automation for advanced packaging and chiplet-based architectures.

This paper presents a hardware-accelerated Advanced Encryption Standard (AES) implementation featuring an 11-stage pipelined architecture and an optimized subkey generation scheme for enhanced performance. This design is implemented in Verilog and verified through waveform analysis. Operating at a maximum clock frequency of 100 MHz, our implementation achieves significant efficiency. The final design occupies an area of 1.44 mm2 and consists of 32,424 standard cells, with a power consumption of 32 mW at the typical corner. Furthermore, the entire design flow, from synthesis to layout (GDSII), is achieved using OpenLane, an open-source Electronic Design Automation (EDA) tool. This democratization of hardware design empowers a wider range of participants, particularly students and researchers, to efficiently implement their designs and gain hands-on experience without the constraints of expensive commercial tools. This fosters innovation and accelerates progress by allowing a broader community to contribute to technological advancements. Index Terms—OpenLane, Open-source , EDA, Pipelined AES, RTL to GDSII

The microcontroller unit (MCU) are mainly used in low power devices, which use limited energy sources such as batteries, energy harvesting, and wireless communications. Therefore, reducing the operating power of the MCU is important to improve energy efficiency by extending battery life or minimizing energy consumption. The MCU is one of the chip designs composed of digital integrated circuits. The clock signal is important element to the MCU. The clock tree, which consists of the clock signal, is directly related to MCU low power operation and performance improvement. Also, chip verification process is important role to improve performance of overall system and reliability to the MCU. However, as the degree of integation of chips, the chip verification process increases complexity and time-comsumption to process many data. Currently, many users dependent on licensed electronic design automation (EDA) tools to ensure high accuracy, minimizing errors in circuit design and improving reliability. The use of licensed EDA tool puts a burden on users including high costs, limited license, difficulty in customization, slow speed, etc. An effective approach to avoid problems by using licensed EDA tools proceeds verification that is unrestricted license and customization for possible using only a register transfer level (RTL) source. In this paper, we propose to predict roughly pre-estimated CTS results using an RTL source in which temporary logic using random buffer insertion is placed before the route process. This paper contributes to reducing MCU operating power and hardware area by performing optimized CTS and minimizing resources according to the RTL structure to be designed.

With the increased level of complexity and market pressures to deliver better results faster and cheaper, Integrated Circuit (IC) companies are looking to innovate and introduce efficiencies into their development process. To improve IC design productivity and time-to-market, this paper introduces an innovative Electronic Design Automation (EDA) tool in order to replicate an existing layout in different technology nodes by automatically porting analog and mixed-signal circuits. Furthermore, the paper presents a case study of the application of the Methodology Assessment Framework (MAF) as an evaluation tool to choose the best suited Software Development Methodology (SDM) for the EDA tool development project.

The Electronic Design Automation (EDA) tools have achieved high degree of maturity and reliability over the years for digital design. The design of analog circuits is a challenge attributed to the existence of multi-dimensional tradeoffs among multiple analog performance metrics like gain, bandwidth, power dissipation, supply voltage, input/output impedances, linearity, voltage swings and noise. The analog design proves to be a significant bottleneck in a System on Chip (SoC) implementation due to lack of automation techniques. To address this issue, the algorithms of the functioning of human brain or soft computing techniques can be gainfully deployed. This work proposes an integrated MaxFit Genetic Algorithm (GA) and GA-SPICE framework to achieve multi-objective optimization of analog design automation. The design of two-stage op-amp is demonstrated in this framework to optimize the objectives of open-loop DC gain, phase margin, unity gain-bandwidth, slew rate, power dissipation and area. The design is performed by proposed MaxFit GA programming of op-amp design equations in MATLAB environment and the design is transmitted seamlessly to LTspice to perform SPICE simulations for design verification. The dynamic fitness evaluation on SPICE generated performance metrics at each iteration of GA programming by transmitting them to MATLAB environment enhances the robustness of analog design significantly.

The mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have almost automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills, design cycle time. This paper presents a novel design flow for constrained optimization of nano-CMOS analog circuits. The proposed analog design flow combines polynomial-regression based models and genetic algorithm for fast optimization. For evaluating the effectiveness of the proposed design flow, power minimization in a 50nm CMOS based current-starved voltage-controlled oscillator (VCO) is carried out, while treating oscillation frequency as a performance constraint. Accurate polynomial-regression based models are developed for power and frequency of the VCO. The goodness-of-fit of the models is evaluated using SSE, RMSE and R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Using these models, we form a constrained optimization problem which is solved using genetic algorithm. The flow achieved 21.67% power savings, with a constraint of frequency ≥ 100 MHz. To the best of the authors' knowledge, this is the first study which approaches a VCO design problem as a mathematical constrained optimization involving the usage of regression based modeling and genetic algorithm.