Electrothermal Effects on Reliability of Vertical Resistive Random Access Memory Array by Parallel Computing

By introducing a capacitor in series (CST), a self‐terminated (ST) operation scheme is proposed to achieve high‐parallel forming of resistive random access memory (RRAM) array with reduced time and energy consumption. Once the RRAM cell is switched to the low‐resistance state, the current is automatically cut off by the capacitor, which can significantly improve the parallelism and energy efficiency. The wire capacitance of interconnect (Cwire) can be utilized as CST, which means there is no addition circuit or process expense for the proposed ST scheme. After successful experimental verification of the proposed ST operation scheme in 1 kb RRAM array, the performance of 1 Gb RRAM memory is evaluated, which shows × 103 improvement in forming time (from 0.6 h to 0.84 s) and × 104 improvement in energy consumption. Moreover, by experimentally leveraging the operation scheme for array forming, the operation current is reduced in subsequent switching process without deteriorating the device reliability, which demonstrates the feasibility of the proposed ST operation scheme and its potential in low power applications.

Homomorphic encryption (HE) is an encryption technology of which encryption and decryption process can be summarized as polynomials modulo multiplication computing with noise. In this paper, HE is firstly implemented on resistive random-access memory (RRAM) arrays, which are utilized as both matrix-vector multiplication (MVM) units and true random number generators (TRNG). Both high stability and good randomness are achieved for MVM and TRNG, respectively, by using different forming schemes, so that two distinct functions can be realized using the same device. Furthermore, the encryption-decryption process for privacy-preserving cloud computing is experimentally implemented on a hardware system with eight 144Kb RRAM arrays. For the whole RRAM array-based encryption-decryption process, small accuracy losses of 0.73% (for SVM) and 1.9% (for CNN) are achieved. This is the first demonstration of encryption computing acceleration with emerging device technology.

Analog memory presents a promising solution in the face of the growing demand for energy-efficient artificial intelligence (AI) at the edge. In this study, we demonstrate efficient deep neural network transfer learning utilizing hardware and algorithm co-optimization in an analog resistive random-access memory (ReRAM) array. For the first time, we illustrate that in open-loop deep neural network (DNN) transfer learning for image classification tasks, convergence rates can be accelerated by approximately 3.5 times through the utilization of co-optimized analog ReRAM hardware and the hardware-aware Tiki-Taka v2 (TTv2) algorithm. A simulation based on statistical 14 nm CMOS ReRAM array data provides insights into the performance of transfer learning on larger network workloads, exhibiting notable improvement over conventional training with random initialization. This study shows that analog DNN transfer learning using an optimized ReRAM array can achieve faster convergence with a smaller dataset compared to training from scratch, thus augmenting AI capability at the edge.

Reducing the process variation is a significant concern for resistive random access memory (RRAM). Due to its ultra-high integration density, RRAM arrays are prone to lithographic variation during the lithography process, introducing electrical variation among different RRAM devices. In this work, an optical physical verification methodology for the RRAM array is developed, and the effects of different layout parameters on important electrical characteristics are systematically investigated. The results indicate that the RRAM devices can be categorized into three clusters according to their locations and lithography environments. The read resistance is more sensitive to the locations in the array (~30%) than SET/RESET voltage (<10%). The increase in the RRAM device length and the application of the optical proximity correction technique can help to reduce the variation to less than 10%, whereas it reduces RRAM read resistance by 4×, resulting in a higher power and area consumption. As such, we provide design guidelines to minimize the electrical variation of RRAM arrays due to the lithography process.

Large-scale colloidal synthesis and integration of uniform-sized molybdenum disulfide (MoS2 ) nanosheets for a flexible resistive random access memory (RRAM) array are presented. RRAM using MoS2 nanosheets shows a ≈10 000 times higher on/off ratio than that based on exfoliated MoS2 . The good uniformity of the MoS2 nanosheets allows wafer-scale system integration of the RRAM array with pressure sensors and quantum-dot light-emitting diodes.

We report flexible resistive random access memory (ReRAM) arrays fabricated by using NiOx/GaN microdisk arrays on graphene films. The ReRAM device was created from discrete GaN microdisk arrays grown on graphene films produced by chemical vapor deposition, followed by deposition of NiOx thin layers and Au metal contacts. The microdisk ReRAM arrays were transferred to flexible plastic substrates by a simple lift-off technique. The electrical and memory characteristics of the ReRAM devices were investigated under bending conditions. Resistive switching characteristics, including cumulative probability, endurance, and retention, were measured. After 1000 bending repetitions, no significant change in the device characteristics was observed. The flexible ReRAM devices, constructed by using only inorganic materials, operated reliably at temperatures as high as 180 °C.

In this paper, the reliability issues of the half-selected cells are investigated in the 1TIR memory array consisting of resistive random access memory (RRAM) and FinFET on 14nm technology node. The impact of electrical stress is discussed under three modes. The leakage current and the saturation current of the transistor would increase and decrease respectively after the stress testing. Considering the both the operation voltage and current of the RRAM, the degradation cannot be neglected. The RRAM cell with ultralow operation voltage and current is required for the practical applications embedded in sub-14-nm technologies. Keywords: OxRRAM, FinFET, stress test, reliability

This work investigates resistive random access memory (ReRAM) data retention after different set/reset endurance cycles on a 50 nm Mega-bit-class Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> ReRAM array. The high resistance state (HRS) before forming and low resistance state (LRS) after forming show the best retention compared with after set/reset programming. When set/reset cycles increase, the LRS retention becomes better, whereas HRS retention gets worse, probably because the filament size becomes larger. Consequently, the retention time of ReRAM is degraded as the device is worn out and the error rate of HRS becomes dominant.

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> times lower power consumption compared to GPU and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

Resistive random access memory (RRAM) has been extensively studied as a promising candidate for neuromorphic computing. So far, high-precision multibit programming of RRAM for neuromorphic systems is done cell-by-cell, which can be very time-consuming. This brief demonstrates a row-by-row parallel program-verify scheme on a fabricated 160-Kb RRAM array using the incremental gate voltage programming (IGVP) method. Statistical analysis indicates that the optimal conductance tuning step size can accelerate the programming process and improve the success rate. Also, for the first time, the fundamental relations between programming success rate, critical path, and parallel efficiency for parallel program-verify methodology on the RRAM array are systematically studied. Moreover, a software-comparable recognition accuracy with only <; 0.3% accuracy loss is experimentally achieved for MNIST data set classification utilizing the proposed parallel program-verify scheme.

As more cloud computing resources are used for machine learning training and inference processes, privacy-preserving techniques that protect data from revealing at the cloud platforms attract increasing interest. Homomorphic encryption (HE) is one of the most promising techniques that enable privacy-preserving machine learning because HE allows data to be evaluated under encrypted forms. However, deep neural network (DNN) implementations using HE are orders of magnitude slower than plaintext implementations. The use of very long polynomials and associated number theoretic transform (NTT) operations for polynomial multiplications is the main bottlenecks of HE implementation for practical uses. This article introduces RRAM number theoretic transform (RM-NTT): a resistive random access memory (RRAM)-based compute-in-memory (CIM) system to accelerate NTT and inverse NTT (INTT) operations. Instead of running fast Fourier transform (FFT)-like algorithms, RM-NTT uses a vector-matrix multiplication (VMM) approach to achieve maximal parallelism during NTT and INTT operations. To improve the efficiency, RM-NTT stores modified forms of the twiddle factors in the RRAM arrays to process NTT/INTT in the same RRAM array and employs a Montgomery reduction algorithm to convert the VMM results. The proposed optimization methods allow RM-NTT to significantly reduce NTT operation latency compared with other NTT accelerators, including both CIM and non-CIM-based designs. The effects of different RM-NTT design parameters and device nonidealities are also discussed.

Resistive random access memory (RRAM) is considered to be a promising compute-in-memory (CIM) platform; however, they tend to lose energy efficiency quickly in high-throughput and high-resolution cases. This paper proposes an analog-oriented RRAM array/read circuits co-design technique to solve the trade-offs between distortion, power consumption, throughput, and chip area. In previous works, the RRAM array is built in a digital mindset that access transistors only serve as switches. Instead, this work investigates a new perspective that utilizes access transistors as common-gate current buffers which reduce the operating current and amplify the output impedance. To further decrease the complexity of peripheral circuits, the idea of In-ADC Computing (IAC) is proposed, which performs shift-add operation together with analog-to-digital conversion. Benefiting from proposed ideas, a pre-trained VGG-8 network based on the CIFAR-10 dataset can be implemented and an accuracy of 87.2% is achieved with 8.9 TOPS/W energy efficiency (for 8-bit MAC operation), demonstrating that the proposed techniques enable low-distortion partial sum results while still be able to operate in a power-efficient way.

Among several types of emerging memory technologies, memristor-based nonvolatile resistive RAM (ReRAM) is currently being investigated as a promising candidate to potentially replace the popular Flash memories, and even other conventional memories such as SRAM and DRAM. At the architectural level, crossbar cell array structure is considered one of the best ways to implement memristor-based ReRAM. This chapter presents an overview of promising ReRAM technologies, their potential benefits, and the key research challenges, with a focus on reduction/oxidation (Redox)-based RAM. It briefly describes the basic operation principles of memristive memory cells, and presents the memristor-based crossbar memory architecture to finally focus on the serious negative impact of the current sneak-paths. Then, two possible methodologies are explored as means to deal with the sneak-path problem, concerning (i) novel storage cell structures, and (ii) modifications in the memory architecture. More specifically, (i) anti-parallel memristive switches are studied as potential cross-point elements in ReRAM arrays, in comparison with anti-serial (complementary) memristive switches. A comprehensive and comparative presentation between them is provided, while commenting on their overall performance and the most appropriate switching characteristics that the structural memristors should have, in order to better fit to memory applications. Moreover, (ii) five alternative architectures (topologies) for passive crossbar ReRAM are presented, which are based on the introduction of a certain percentage of insulating nodes spread out inside the array according to specific distribution patterns. Both approaches enable crossbar memory arrays without select devices, thus they simplify the array fabrication process and could be well-suited for future data storage applications. Finally, XbarSim, a GUI-based educational simulation tool aiming to serve students/researchers who wish to explore and study the memristive crossbar circuit architecture, is presented.

To conquer the von Neumann bottleneck, it is necessary to shift computation to the place where data resides. In this work, we present a methodology to move the comparator circuit to the memory array. A binary comparator is implemented in a transistor-accessed ReRAM (Resistive Random Access Mem-ory) array using majority logic. The majority primitive is a better logic primitive than NAND/NOR/IMPLY primitives for arithmetic intensive operations and also can be realized in memory array efficiently as a READ operation. Using Majority gates and vast gate-level parallelism in the array, comparator is implemented optimally, latency and energy-wise. Using the methodology presented for 1-bit and 8-bit, any n-bit comparator can be realized in 6 + 4log <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> n cycles. Moreover, a general transistor-accessed memory array can be used to implement the proposed comparator without the need for any supreme modifications to the memory peripherals and is efficient as well in terms of energy.

We present the first demonstration of 1T4R Resistive RAM (RRAM) array storing two bits per RRAM cell. Our HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> - based RRAM is built using a logic foundry technology that is fully compatible with the CMOS back-end process. We present a new approach to program RRAM cells using gradual SET/RESET pulses while minimizing disturbances on adjacent cells (belonging to the same 1T4R RRAM structure) - this new approach makes our multiple-bits-per-cell 1T4R RRAM array demonstration possible. We report over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cycles of endurance and a projected 10-year retention at 120°C. Using measured data from our 2 bits- per-cell 1T4R RRAM array, we analyze multiple deep learning applications and demonstrate high degrees of inference accuracy (within 0.01% of ideal values).