Enabling and Exploiting Flexible Task Assignment on GPU through SM-Centric Program Transformations

The massive parallelism present in GPUs comes at the cost of reduced L1 and L2 cache sizes per thread, leading to serious cache contention problems such as thrashing. Hence, the data access locality of an application should be considered during thread scheduling to improve execution time and energy consumption. Recent works have tried to use the locality behavior of regular and structured applications in thread scheduling, but the difficult case of irregular and unstructured parallel applications remains to be explored. We present PAVER , a P riority- A ware V ertex schedul ER , which takes a graph-theoretic approach toward thread scheduling. We analyze the cache locality behavior among thread blocks ( TBs ) through a just-in-time compilation, and represent the problem using a graph representing the TBs and the locality among them. This graph is then partitioned to TB groups that display maximum data sharing, which are then assigned to the same streaming multiprocessor by the locality-aware TB scheduler. Through exhaustive simulation in Fermi, Pascal, and Volta architectures using a number of scheduling techniques, we show that PAVER reduces L2 accesses by 43.3%, 48.5%, and 40.21% and increases the average performance benefit by 29%, 49.1%, and 41.2% for the benchmarks with high inter-TB locality.

The demand for multitasking on graphics processing units (GPUs) is constantly increasing as they have become one of the default components on modern computer systems along with traditional processors (CPUs). Preemptive multitasking on CPUs has been primarily supported through context switching. However, the same preemption strategy incurs substantial overhead due to the large context in GPUs. The overhead comes in two dimensions: a preempting kernel suffers from a long preemption latency, and the system throughput is wasted during the switch. Without precise control over the large preemption overhead, multitasking on GPUs has little use for applications with strict latency requirements. In this paper, we propose Chimera, a collaborative preemption approach that can precisely control the overhead for multitasking on GPUs. Chimera first introduces streaming multiprocessor (SM) flushing, which can instantly preempt an SM by detecting and exploiting idempotent execution. Chimera utilizes flushing collaboratively with two previously proposed preemption techniques for GPUs, namely context switching and draining to minimize throughput overhead while achieving a required preemption latency. Evaluations show that Chimera violates the deadline for only 0.2% of preemption requests when a 15us preemption latency constraint is used. For multi-programmed workloads, Chimera can improve the average normalized turnaround time by 5.5x, and system throughput by 12.2%.

The increasing amount of trajectory data facilitates a wide spectrum of practical applications. In many such applications, large numbers of trajectory range and similarity queries are issued continuously, which calls for high-throughput trajectory query processing. Traditional in-memory databases lack considerations of the unique features of trajectories, thus suffering from inferior performance. Existing trajectory query processing systems are typically designed for only one type of trajectory queries, i.e., either range or similarity query, but not for both. Inspired by the massive parallelism on GPUs, in this paper, we develop a GPU-accelerated framework, named GAT, to support both types of trajectory queries (i.e., both range and similarity queries) with high throughput. For similarity queries, we adopt the Edit Distance on Real sequence (EDR) as the similarity measure which is accurate and robust to noise in real-world trajectories. GAT employs a GPU-friendly index called GTIDX to effectively filter invalid trajectories for both range and similarity queries, and exploits the GPU to perform parallel verifications. To accelerate the verification process on the GPU, we apply the Morton-based encoding method to reorganize trajectory points and facilitate coalesced data accesses for individual point data in global memory, which reduces the global memory bandwidth requirement significantly. We also propose a technique of grouping size-varying cells into balanced blocks with similar numbers of trajectory points, to achieve load balancing among the Streaming Multiprocessors (SMs) of the GPU. We conduct extensive experiments to evaluate the performance of GAT using two real-life trajectory datasets. The results show that GAT is scalable and achieves high throughput with acceptable indexing cost.

GPUs are widely adopted in HPC and cloud computing platforms to accelerate general-purpose workloads. However, modern GPUs do not support flexible preemption, leading to performance and priority inversion problems in multi-tasking environments. In this paper, we propose and develop FLEP, the first software system that enables flexible kernel preemption and kernel scheduling on commodity GPUs. The FLEP compilation engine transforms the GPU program into preemptable forms, which can be interrupted during execution and yield all or part of the streaming multi-processors (SMs) in the GPU. The FLEP runtime engine intercepts all kernel invocations and determines which kernels and how those kernels should be preempted and scheduled. Experimental results on two-kernel co-runs demonstrate up to 24.2X speedup for high-priority kernels and up to 27X improvement on normalized average turnaround time for kernels with the same priority. FLEP reduces the preemption latency by up to 41% compared to yielding the whole GPU when the waiting kernels only need several SMs. With all the benefits, FLEP only introduces 2.5% runtime overhead, which is substantially lower than the kernel slicing approach.

This paper analyses busy burst (BB) enabled interference avoidance for multi-user orthogonal frequency division multiple access (OFDMA) in a Manhattan grid deployment scenario. Upon successful reception of data, the receiver transmits a BB in a time-multiplexed mini-slot. Exploiting the channel reciprocity of time division duplex (TDD), an exclusion region around a victim receiver is established, where potential transmitters are denied access to reserved resources. The size of the exclusion region is determined by a threshold parameter, known to the entire network. System level simulations compare the system and user throughput of BB enabled interference avoidance with greedy resource allocation that does not attempt to avoid interference. It is shown that by adjusting the BB threshold parameter, system throughput can be traded with fairness in terms of cell-edge user throughput. By tuning the BB threshold, either up to 45% increase in system throughput or up to 7-fold increase in cell-edge user throughput are feasible compared to greedy resource allocation. Moreover, by an appropriate adjustment of the BB power further gains in system throughput without compromising fairness are achieved.

As graphics processing units (GPUs) are broadly adopted, running multiple applications on a GPU at the same time is beginning to attract wide attention. Recent proposals on multitasking GPUs have focused on either spatial multitasking, which partitions GPU resource at a streaming multiprocessor (SM) granularity, or simultaneous multikernel (SMK), which runs multiple kernels on the same SM. However, multitasking performance varies heavily depending on the resource partitions within each scheme, and the application mixes. In this paper, we propose GPU Maestro that performs dynamic resource management for efficient utilization of multitasking GPUs. GPU Maestro can discover the best performing GPU resource partition exploiting both spatial multitasking and SMK. Furthermore, dynamism within a kernel and interference between the kernels are automatically considered because GPU Maestro finds the best performing partition through direct measurements. Evaluations show that GPU Maestro can improve average system throughput by 20.2% and 13.9% over the baseline spatial multitasking and SMK, respectively.

Graphics processing units(GPUs) have been increasingly used to accelerate general purpose computations. By exploiting massive thread-level parallelism (TLP), GPUs can achieve high throughput as well as memory latency hiding. As a result, a very large register file (RF) is typically required to enable fast and low-cost context switching between tens of thousands of active threads. However, RF resource is still insufficient to enable all thread level parallelism and the lack of RF resources can hurt performance by limiting the occupancy of GPU threads. Moreover, if the available RF capacity can not fit the requirement of a thread block, GPU needs to fetch some variables from local memory which may lead to long memory access latencies. By observing that a large percentage of computed results actually have fewer significant bits compared to the full width of a 32-bit register for many GPGPU applications, we propose a GPU register packing scheme to dynamically exploit narrowwidth operands and pack multiple operands into a single fullwidth register. By using dynamically register packing, more RF space is available which allows GPU to enable more TLP through assigning additional thread blocks on SMs (Streaming Multiprocessors) and thus improve performance. The experimental results show that our GPU register packing scheme can achieve up to 1.96X speedup and 1.18X on average.

In the literature on the relationship between participation in decision making and performance, a tell‐and‐sell strategy is considered a viable alternative to participation. In contrast, we argue that in organizational settings, when a sensitive and important issue is at stake, participation of a form to be characterized as formal, long term, direct, and with a high degree of participant influence is more effective than a tell‐and‐sell strategy. Using a quasi‐experimental design with a participation, a tell‐and‐sell, and a control condition, a ProMES performance management system was implemented in the field service department of a Dutch supplier of photocopiers. Outcome feedback to individual technicians resulted in an average performance increase in the participation condition that was significantly higher than the increase found in the tell‐and‐sell condition. Satisfaction with the program, and the perceived usefulness of the feedback, were significantly higher in the participation condition. In both experimental conditions, the performance increase was significant compared to the control condition. An explanation for these findings is discussed, as are implications for theory and practice. Copyright © 2004 John Wiley & Sons, Ltd.

Here, we report the test of solution-processed nickel (Ni)-alloyed iron disulfide (FeS2) pyrite nanocrystals (NCs) as back contact interface layer in cadmium telluride (CdTe) solar cells. The alloyed NCs were synthesized using the hot-injection colloidal method, and the thin films were fabricated using layerby-layer drop-cast method as the back contacts to the CdTe solar cells. Based on this study, the average increase in device performance observed was 6% with Ni0.05Fe0.95S2 and Ni0.1Fe0.9S2 NCs compared to standard copper/gold (Cu/Au) back contacts while the device performance was sharply reduced with ≥ 20% Ni-alloyed iron pyrite NCs.

A Mobile Ad Hoc Network (MANET) protocol requires proper settings to perform data transmission optimally. To overcome this problem, it is necessary to select the correct routing protocol and use the routing protocol’s default parameter values. This study examined the effect of route request parameters, such as RREQ_RETRIES and MAX_RREQ_TIMOUT, on the Ad Hoc On-demand Distance Vector (AODV) protocol, which was then compared with the default AODV performance Optimized Link State Routing (OLSR) protocols. The performance metrics used for measuring performance were Packet Delivery Ratio (PDR), throughput, delay, packet loss, energy consumption, and routing overhead. The results show that the OLSR protocol has a smaller delay than the AODV protocol, while in other measurements, the AODV protocol is better than OLSR. By reducing the combination value of RREQ_RETRIES, MAX_RREQ_TIMEOUT in AODV routing to (2, 10 s) and (3, 5 s), the protocol’s performance can be improved. The two combinations result in an average increase in throughput performance of 3.09%, a decrease in delay of 17.7%, a decrease in packet loss of 27.15%, and an increase in PDR of 4.8%. For variations in the speed of movement of nodes, 20 m/s has the best performance, while 5 m/s has the worst performance.

Building the quality of education continues to be done, both by the government and the school as education providers. In an effort to meet the needs and demands of society on the quality of education and simultaneously as a response to the changes of life very quickly in the era of globalization. For that reason researchers need research on improving the quality of teaching and learning process through supervisory function in the integrated quality management in the District Kepengawasan Cluster 05 District Magersari Mojokerto City.
 This research uses action research for three cycles. Each cycle consists of one meeting each of which consists of four stages: design, activity and observation of reflection and revision. The target of this research is Master of Kepengawasan District School Cluster 05 Magersari Subdistrict Mojokerto City 15 people. The data obtained in the form of the results of supervision assessment of teaching and learning process.
 The success of the learning process in cycle III shows that the cycle can be stopped because it has met the target of> 70%. This is evident from the average increase in teacher performance per cycle.
 The conclusions of this research are: The quality of teaching and learning process through supervisory function in integrated quality management in Kepengawasan Area School Cluster 05 Magersari Sub-district Mojokerto City has increased, it can be seen from the average of teacher performance improvement from 65,87 percent in cycle I, to 76.67 in Cycle II and increased to 82.86 percent in Cycle III.

Performance effective pre-scheduling strategy for heterogeneous grid systems in the master slave paradigm

Locality based warp scheduling in GPGPUs

Blocking locks are commonly used in parallel programs to improve application performance and system throughput. However, most implementations of such locks suffer from two major problems-latency and scalability. We propose an implementation of blocking locks using scheduler adaptation which exploits the interaction between thread schedulers and locks. By experimentation using well-known multiprocessor applications on a KSR2 multiprocessor, we demonstrate how such an implementation considerably reduces the latency, and improves the scalability of blocking locks.

Iterative stencils represent the core computational kernel of many applications belonging to different domains, from scientific computing to finance. Given the complex dependencies and the low computation to memory access ratio, this kernels represent a challenging acceleration target on every architecture. This is especially true for FPGAs, whose direct hardware execution offers the possibility for high performance and power efficiency, but where the non-fixed architecture can lead to very large solutions spaces to be explored. In this work, we build upon an FPGA-based acceleration methodology for iterative stencil algorithms previously presented, where we provide a dataflow architectural template that implements optimal on-chip buffering and is able to increase almost linearly in performance using a scaling technique denoted as iterations queuing. In particular, we propose a set of design improvements and we elaborate an accurate analytical performance model that can be used to support the exploration of the design space. Experimental results obtained implementing a set of benchmarks from different application domains on a Xilinx VC707 board show an average performance and power efficiency increase over the previous work of respectively 22.8x and 9.9x, and a prediction error that is on average 0.5%.