Enabling energy efficient Hybrid Memory Cube systems with erasure codes

Backgate biasing is a promising technique for highspeed systems. Leakage can be reduced during standby periods by reverse bias while adequate bias in active mode can balance process and temperature variations. This technique introduces no delay penalty in active mode but slow wake up time results in system performance degradation. In this paper, a backgate bias accelerator achieving 24ns/V sleep-to-active mode transition rate is demonstrated in a 90 nm CMOS technology. The circuit performs auto-calibration of the transition time as a function of the Sleep and Active mode backgate bias voltages. Those can therefore be tuned on-chip according to process variations and/or operating conditions. The accelerator occupies less than 2.5% of the total chip area, consumes 600μW during the transitions and doesn’t add any bias current during active and sleep modes.

The increasing memory requirements of big data applications have been driving the precipitous growth of memory capacity in server systems. To maximize the efficiency of external memory, HW-based memory compression techniques have been proposed to increase effective memory capacity. Although such memory compression techniques can improve the memory efficiency significantly, a critical trade-off exists in the HW-based compression techniques. As the memory blocks need to be decompressed as quickly as possible to serve cache misses, latency-optimized techniques apply compression at the cacheline granularity, achieving the decompression latency of less than a few cycles. However, such latency-optimized techniques can lose the potential high compression ratios of capacity-optimized techniques, which compress larger memory blocks with longer latency algorithms.Considering the fundamental trade-off in the memory compression, this paper proposes a transparent dual memory compression (DMC) architecture, which selectively uses two compression algorithms with distinct latency and compression characteristics. Exploiting the locality of memory accesses, the proposed architecture compresses less frequently accessed blocks with a capacity-optimized compression algorithm, while keeping recently accessed blocks compressed with a latency-optimized one. Furthermore, instead of relying on the support from the virtual memory system to locate compressed memory blocks, the study advocates a HW-based translation between the uncompressed address space and compressed physical space. This OS-transparent approach eliminates conflicts between compression efficiency and large page support adopted to reduce TLB misses. The proposed compression architecture is applied to the Hybrid Memory Cube (HMC) with a logic layer under the stacked DRAMs. The experimental results show that the proposed compression architecture provides 54% higher compression ratio than the state-of-the-art latency-optimized technique, with no performance degradation over the baseline system without compression.

With increasing demand for distributed intelligent physical systems performing big data analytics on the field and in real-time, processing-in-memory (PIM) architectures integrating 3D-stacked memory and logic layers could provide higher performance and energy efficiency. Towards this end, the PIM design requires principled and rigorous optimization strategies to identify interactions and manage data movement across different vaults. In this paper, we introduce Prometheus, a novel PIM-based framework that constructs a comprehensive model of computation and communication (MoCC) based on a static and dynamic compilation of an application. Firstly, by adopting a low level virtual machine (LLVM) intermediate representation (IR), an input application is modeled as a two-layered graph consisting of (i) a computation layer in which the nodes denote computation IR instructions and edges denote data dependencies among instructions, and (ii) a communication layer in which the nodes denote memory operations (e.g., load/store) and edges represent memory dependencies detected by alias analysis. Secondly, we develop an optimization framework that partitions the multi-layer network into processing communities within which the computational workload is maximized while balancing the load among computational clusters. Thirdly, we propose a community-to-vault mapping algorithm for designing a scalable hybrid memory cube (HMC)-based system where vaults are interconnected through a network-on-chip (NoC) approach rather than a crossbar architecture. This ensures scalability to hundreds of vaults in each cube. Experimental results demonstrate that Prometheus consisting of 64 HMC-based vaults improves system performance by 9.8x and achieves 2.3x energy reduction, compared to conventional systems.

Convolutional/Deep Neural Networks (CNNs/DNNs) are rapidly growing workloads for the emerging AI-based systems. The gap between the processing speed and the memory-access latency in multi-core systems affects the performance and energy efficiency of the CNN/DNN tasks. This article aims to alleviate this gap by providing a simple and yet efficient near-memory accelerator-based system that expedites the CNN inference. Towards this goal, we first design an efficient parallel algorithm to accelerate CNN/DNN tasks. The data is partitioned across the multiple memory channels (vaults) to assist in the execution of the parallel algorithm. Second, we design a hardware unit, namely the convolutional logic unit (CLU), which implements the parallel algorithm. To optimize the inference, the CLU is designed, and it works in three phases for layer-wise processing of data. Last, to harness the benefits of near-memory processing (NMP), we integrate homogeneous CLUs on the logic layer of the 3D memory, specifically the Hybrid Memory Cube (HMC). The combined effect of these results in a high-performing and energy-efficient system for CNNs/DNNs. The proposed system achieves a substantial gain in the performance and energy reduction compared to multi-core CPU- and GPU-based systems with a minimal area overhead of 2.37%.

The energy efficiency of space heaters is rated by Annual Fuel Utilization Efficiency (AFUE) governed by the Department of Energy in the United States which is a simple ratio of usable heat and fuel usage of a single heating device. It doesn't consider the overall performance of the heating system including not only the heating devices but also the characteristics of the building in different applications. The current AFUE method calculates only the energy efficiency which is thermodynamics first law efficiency. In this research, the systematic efficiency of a heating system rather than simple device efficiency has been defined and investigated. The systematic efficiency considers the overall efficiency of the whole heating system and it varies in the different applications even though with the same heating device. So it represents the performance of the system more precisely. Analytical models have been built to calculate both the systematic energy efficiency and exergy efficiency, and to evaluate the systematic energy and exergy efficiency of heating systems for direct fired and indirect fired heaters. Efficiency performances of the systems with these two types of heaters are compared. Sensitivities of input parameters for systematic energy efficiency are studied to show the impact towards systematic energy efficiency. Indoor carbon dioxide concentration level of direct fired heating system is also studied. In a case study, results show that systematic energy efficiency of indirect fired heating system is always constant at heater device efficiency which is 80\% while systematic energy efficiency of direct fired heating system varies from 40%-92% under different condition (heat loss coefficient, ambient temperature and air change requirement), indicating that simple device efficiency is not capable to evaluate the overall performance of heating system. New efficiency method such as systematic energy efficiency used in this research is needed to better describe the performance of the heating system. Results of indoor carbon dioxide level of direct fired heating system, from 1000 to 4500 PPM under different conditions, show that indoor air quality needs to be considered while using direct fired heating.

The dramatic increase in the number of heterogeneous computing architectures (HCAs) which include CPUs, GPUs, TPUs, FPGAs, and new neuromorphic processors has transformed the high-performance computing (HPC) and artificial intelligence (AI) workloads. As the complexity of architecture increases there is corresponding uncertainty on reliability and performance checks, particularly when systems are incorporated with different processing elements, interconnections, and memory levels. Modern non-deterministic or non-stochastic heterogeneous environments are associated with traditional reliability models that feel great necessity to model nonlinear interdependencies between components. The current paper proposes an innovative AI-based modeling framework that would be capable of measuring system reliability and performance indicators in the context of HCAs. The suggested solution merges Deep Neural Networks (DNNs), Bayesian Inference Models, and the strategies of Reinforcement Learning (RL) to forecast the increase of the system reliability, the performance bottlenecks, and the mean time between failures (MTBF) at the system level. To train AI models that can capture the multi-domain interactions of computation, communication, and thermal dynamics, a large-scale simulation dataset was created with synthetic benchmarks, actual workloads (SPEC ACCEL, MLPerf, HPCG), unlikely fault profiles, and injected fault profiles to have AI models that are trained to simulate interactions in large-scale systems. The approach puts the feature engineering of runtime telemetry (e.g., power, temperature, utilization) and hardware counters (e.g., instruction-level parallelism, cache miss rates) to construct predictive and adaptive reliability estimators. As opposed to the traditional models, our AI-based system advances its state dynamically with online learning methods of training, allowing its internal state to identify fault and self-optimize it. Findings suggest that the suggested AI system can make accurate predictions in both system performance degradation and reliability estimates with a success level of 96.8 and 94.2 per cent respectively when operating in a heterogeneous environment. Comparative research with classical models of reliability, i.e. Markov and Weibull-based models reveal high gains on adaptability, precision and generalization. Moreover, the optimization using reinforcement learning provided a 1525 percentage ratio in task scheduling performance expressed in a limited thermal and power budget. This article adds to the increasing overlap between system modeling based on AI and the optimization of heterogeneous computing, sets the stage of the introduction of new intelligent reliability management of data centers, autonomous computing systems, and HPC infrastructure

This paper documents an investigation into the performance and thermal efficiency of an air-cycle Environmental Control System (ECS) artificially injected with common operational failure modes. A two-wheel bootstrap system is taken from an in-service military fast-jet and installed in a bespoke Ground Test Facility (GTF) at the ECS Research Facility, Loughborough University, UK. The failure modes investigated are bleed air blockages in the intercooler and in the low-pressure water extractor, as well as positional inaccuracy in cycle bypass control valves. The full range of degradation in each fault is considered, allowing the quantification of overall system performance degradation. The performance of the system is found to be insensitive to moderate bleed air blockages (up to 80% by pipe cross-section area), whilst blockages at low pressure are more detrimental to cycle performance than blockages at high pressure. The cycle and/or control system will self-regulate around most degrading-type faults. This particular system is most sensitive to a failure at one bypass valve, where the hardware allows partial redundancy of the valve but the control system does not.

With the progress of deep submicron technology, power consumption and temperature related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management. On the other hand, application of thermal management is accompanied by disturbance of system integrity and degradation of system performance. In this paper the authors propose to precompute and proactively manage on-chip temperature of systems based on Networks-on-Chip (NoCs). Thereby, traditional reactive approaches, utilizing the NoC infrastructure to perform thermal management, can be replaced. This results not only in shorter response times for application of management measures and a reduction of temperature and thermal imbalances, but also in less impairment of system integrity and performance. The systematic analysis of simulations conducted for NoC sizes ranging from 2x2 to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile.

In this article, we consider a stochastic model of wireless sensor networks (WSNs) in which each sensor node randomly and alternatively stays in an active mode or a sleep mode. The active mode consists of two phases, called the full-active phase and the semi-active phase. When a referenced sensor node is in the full-active phase of the active mode, it may sense data packets, transmit the sensed packets, receive packets, and relay the received packets. However, when the phase of the sensor node switches from the full active phase to the semi-active phase, it is only able to transmit/relay data. When the referenced sensor node is in a sleep mode, it does not interact with the external world. In this article, first, we develop a stochastic model for the sensor node of a WSN, and then we derive an explicit expression of the stationary distribution of the number of data packets in the sensor node. Furthermore, we figure out some important performance measures, including the sensor node’s energy consumption for transmission, the energy consumption of the sensor operations, and the average energy consumption of the sensor node in a cycle of active and sleep modes. Also, a numerical analysis is provided to validate the proposed model and the results obtained. The novel aspects of our research are the development of a stochastic model for WSN with active and sleep features and the development of important analytical formulae for evaluating the energy consumption of a WSN. These results are expected to be useful as significant contributions to the fundamental theory of the design of various WSNs with active and sleep mode considerations.

The increasing vulnerability of networked control systems (NCSs) to cyber-physical attacks necessitates the development of adaptive security strategies to mitigate risks and ensure system stability. This study explores the Markovian switching-based security strategies for interconnected NCSs, incorporating stochastic optimization and linear matrix inequality (LMI)-based approaches to enhance system resilience against adversarial threats. The primary objectives include formulating a robust mathematical framework that integrates Markovian jump linear systems (MJLSs) with dynamic security mechanisms, designing LMI-based security constraints for stability assurance, and validating the proposed approach through numerical simulations. The study models various cyber-attacks, including denial-of-service (DoS), replay attacks, and hybrid attacks, while employing Markovian switching dynamics to represent system transitions under attack conditions. The results reveal that persistent and hybrid attacks cause significant degradation in system performance, lowering the stability index and control efficiency while increasing response time. Statistical analysis using ANOVA confirms the significant impact of attack types on system stability and efficiency. The findings support the hypothesis that adaptive Markovian switching strategies improve system resilience compared to conventional static security methods. This research contributes to the development of real-time security frameworks for cyber-physical systems, offering practical recommendations for integrating AI-driven detection algorithms, cryptographic security, and hierarchical control strategies to counter evolving cyber threats in industrial automation and smart infrastructures.

In the IoT for multi-sensor node application [1], there are demanded both high-performance for computation in an active mode, and an ultra-low standby power in a sleep mode for longtime buttery life in the energy efficient system. Ultra-low standby MCU with embedded NVM using 90 nm CMOS technology is also reported [2], but its SRAM cache is not sufficient for applying imaging processing which requires large memory capacity with imaging sensors in edge computing. Embedded SRAMs can be achieved fast read/write access within a few nanoseconds, but consume standby leakage power for data retention, being dominant power in the sleep mode. To reduce the standby leakage power of embedded SRAMs, the source bias design technique with power-gating is introduced on a bulk CMOS device [3]. In the resume standby (RS) mode, the VSS source bias control for SRAM array is demonstrated as an effective SRAM leakage power reduction. Besides, once the large SRAM array are into the resume standby mode, it takes long time to wake-up again. It is not applicable for high-speed CPU operation. Then, a fast resume standby mode (FRS) for cache memories is proposed to wake-up as much as fast. In that FRS mode, the power supply for SRAM peripheral is cutoff but SRAM array is keeping with a VDD supply. Each standby mode and its circuit diagram are summarized in Fig. 1. Meanwhile, dopant-less channel fully-depleted (FD) silicon-on-insulator (SOI) device is proposed [4]–[6] to improve the performance, power, and area (PPA) of embedded SRAMs. FD-SOI enables to control the back-bias (BB) dynamically under the buried-oxide (BOX) to reduce leakage current and/or to improve performance by applying reverse or forward bias, respectively. Fig. 2 presents the block diagram of BB control scheme for voltage scaling in IoT application with FD-SOI structure [7]–[9]. BBs for NMOS (VBN) and PMOS (VBP) can be applied individually by VBB generator (VBB Gen.) circuit. Four operation modes for smart IoT applications are considered. High-performance, normal, low-power operating modes are introduced, along with the required loads in the system. The sleep mode with SRAM data retention for long-term waiting in the sensor nodes is also proposed. Each supply voltage and BB is also shown in Fig. 2. The comparison of embedded SRAM leakage power is shown in Fig. 3.

We study the problem of optimizing the performance of a system shared by selfish, noncooperative users. We consider the concrete setting of scheduling jobs on a set of shared machines with load-dependent latency functions specifying the length of time necessary to complete a job; we measure system performance by the total latency of the system.Assigning jobs according to the selfish interests of individual users (who wish to minimize only the latency that their own jobs experience) typically results in suboptimal system performance. However, in many systems of this type there is a mixture of “selfishly controlled” and “centrally controlled” jobs; as the assignment of centrally controlled jobs will influence the subsequent actions by selfish users, we aspire to contain the degradation in system performance due to selfish behavior by scheduling the centrally controlled jobs in the best possible way.We formulate this goal as an optimization problem via Stackelberg games, games in which one player acts a leader (here, the centralized authority interested in optimizing system performance) and the rest as followers (the selfish users). The problem is then to compute a strategy for the leader (a em Stackelberg strategy) that induces the followers to react in a way that (at least approximately) minimizes the total latency in the system.In this paper, we prove that it is NP-hard to compute the optimal Stackelberg strategy and present simple strategies with provable performance guarantees. More precisely, we give a simple algorithm that computes a strategy inducing a job assignment with total latency no more than a constant times that of the optimal assignment of all of the jobs; in the absence of centrally controlled jobs and a Stackelberg strategy, no result of this type is possible.

We discuss the implementation of a face verification system on smart card and study the trade-off between performance and computational complexity. In order to establish the system limitations, a study was performed on BANCA and XM2VTS databases. The results of the experiments performed show that the choice of a fixed precision data type does not affect system performance very much but can speed up the verification process. Moreover, the use of less than 8 bits per pixel gray-scale image resolution does not necessarily result in a degradation of system performance. We show that, for both databases, image resolution can be reduced without degrading system performance. However, the actual optimal settings will depend on application scenario.KeywordsFace ImageSmart CardFalse Rejection RateBiometric TemplateFace VerificationThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Previous work on the discrimination of transducers against reverberation has been extended to include the influence of beamwidth and multiple transmisisons. The directivity index against reverberation is expressed in terms of an ideal searchlight beamwidth that is defined as having a response of unity within the region bounded by its beam and a response of zero elsewhere. This ideal beamwidth is found by considering the total received reverberation power from a specific projector-receiver combination. Two situations are treated: namely, a single transmission and several transmissions. For a single transmission, various transmitting and receiving beamwidths are considered in order to determine the degradation in system performance when transmitting beam dimensions differ from those of the receiving beams. The sensitivity of these results to minor-lobe levels is demonstrated. The findings are then generalized by expressing the multiple-transmission case in terms of an equivalent single transmission. The consequences of the theory are compared with observed sea data and are shown to depend upon reverberation decay rate, and hence upon water depth. Finally, the relation between search rate, beamwidth, and system performance is developed.

Physical Carrier Sensing plays a crucial role in the effectiveness of CSMA-based MAC protocols, yet its properties and impact on the system performance under slow fading channel have not been well understood. We demonstrate that carrier sensing can be highly unreliable even within the "carrier sensing range" and the channel is largely stable during a transmission between slowly moving mobile stations. Then we formulate the carrier sensing outage probability between competing mobile stations and propose a model to estimate the frame error rate and normalized throughput of a saturated IEEE 802.11 DCF single-hop ad-hoc network. Our model is validated via extensive simulations using Qualnet. The numerical and simulation results reveal substantial degradation in system performance with a small amount of carrier sensing outage.