Energy-Aware Non-Preemptive Task Scheduling With Deadline Constraint in DVFS-Enabled Heterogeneous Clusters

The functionality of embedded systems is ever growing. The computational power of embedded systems is growing to match this demand, with embedded multiprocessor systems becoming more common. The limitations of embedded systems are not always related to chip size but are commonly due to energy and/or power constraints. While it can be possible to embed a more powerful Multiprocessor System on Chip (MPSoC), it is not always possible to provide an energy or power supply that meets its demands within the device’s size and weight requirements. Power management through Dynamic Voltage and Frequency Scaling (DVFS) enables the device to be run at less than its maximum voltage and frequency, allowing high computational capability when necessary while conserving power at other times. Embedded systems commonly perform real-time functionality. A real-time application has an associated formal model to verify that it meets its timing requirements. This formal model is used to perform a worst-case timing analysis to ensure that the application meets its requirements. These models incorporate the worst-case timing of the application’s computation and communication. Timing changes due to power management must also be taken into account, complicating the verification process. The drive for evermore functionality has led to mixed time-criticality systems, in which multiple applications of various timing criticalities share the same (hardware) resources. This complicates the verification process further as the timing interference due to shared resource contention must be taken into account. A monolithic verification effort is therefore traditionally required after system integration and must be carried out again if any modifications are made that affect the timing of any of the applications. The problem that we aim to solve in this work is to enable real-time applications to perform independent execution and power management without violating their timing requirements or invalidating the timing verification of concurrently executing applications. To solve this problem, we contribute the Composable and Predictable Microkernel (CoMik) to composably and predictably virtualise processors. When used in combination with composable and predictable memory controllers and interconnect (as provided by the Composable and Predictable System-on-Chip (CompSOC) platform), these virtual processors cannot interfere with each other’s timing by even a single cycle. If whatever executes on the virtual processors (e.g. an Operating System (OS) or an application directly) has a real-time requirement, it can be verified independently of whatever executes on the concurrent virtual processors and other virtual resources. To enable formally analysable application execution, we contribute the Predictable Operating System (POSe) that enables dataflow applications to be executed on the (virtualised) processor. We contribute a combined application and platform dataflow graph, including an algorithm to automate this process. When annotated with worst-case timings, the combined application and system graph is then used to verify that the application meets its timing requirement. If the application’s performance is better than its requirement (e.g. when the input or platform behaviour are better than worst case), its performance can be reduced using DVFS to achieve a reduction in power consumption. We contribute an off-line convex optimisation that uses the combined application and platform dataflow model to derive static run-time operating frequency levels to achieve low power consumption. The off-line technique is able to exploit static slack in the schedule, but not dynamic run-time slack due to variations in task execution times. Before dynamic slack can be used it must be possible to observe it. For this purpose, CoMik provides independent power, energy and timing accounting per virtual processor. This enables each virtual processor to be assigned individual power and energy budgets and POSe applications to be assigned timing budgets. We contribute a description and model of how energy and power budgets can be distributed between multiple virtual processors, enabling whatever executes on the virtual processor to perform composable independent power-management without affecting the ability of other virtual processors from using their entire budget allocation. Using CoMik’s accounting infrastructure, we also demonstrate how the quality of applications can be dynamically scaled to assist meeting timing, energy or power requirements. We further contribute a distributed dynamic power management policy that enables dataflow applications that are mapped onto multiple (virtual) processors to make distributed dynamic slack observations and local power-management decisions. We demonstrate the applicability of the presented techniques on an implemented Field Programmable Gate Array (FPGA) prototype of a CompSOC hardware platform instance, using an H.263 decoder as a case-study application. We show that our techniques do not only work in theory, but that they are also implementable and implemented.

For energy efficient scheduling of task graphs on multiprocessors, dynamic voltage and frequency scaling (DVFS) and duplication are two widely used techniques. DVFS is generally used to utilize the execution slack by lowering the voltage and frequency of a task to decrease the dynamic energy consumption. Whereas duplication decreases the schedule length and communication energy consumption by replicating certain dependent tasks to avoid communication delays. However, while making decisions on DVFS and duplication for a task, the static energy consumption is mostly overlooked. With chip technologies reducing to a few nano meters, static energy consumption due to leakage current has become important. This article proposes a novel polynomial time heuristic that uses both DVFS and duplication to optimize static energy consumption along with dynamic and communication energy when scheduling task graphs on heterogeneous multiprocessors. The proposed list scheduling algorithm also balances schedule length with energy consumption using proposed normalized difference parameters while making scheduling decisions for a particular task. The results demonstrate the ability of the proposed algorithm to decrease the overall energy consumption with an improved or comparable schedule length as compared with other algorithms in various scenarios.

Energy efficiency and energy proportional computing have become major constraints in the design of modern exascale platforms. Dynamic voltage and frequency scaling (DVFS) is one of the most commonly used and effective techniques to dynamically reduce power consumption based on workload characteristics. Many energy-saving strategies, however, employ DVFS without considering its applicability level in a given multicore processor. The present work demonstrates that disregarding the DVFS granularity as a design constraint while developing energy-saving strategies may reduce the efficacy of the strategy for certain application classes. Specifically, DVFS applicability levels (called granularities) are determined here for three different Intel processor microarchitectures. Then, the degradation in energy savings is evaluated if the DVFS granularity is disregarded. Experiments were conducted on the widely used quantum chemistry packages, General Atomic and Molecular Electronic Structure System (GAMESS) and NWChem, and show that, for granularity unaware energy-saving techniques, the overall energy consumption may increase by as much as 19%.

Many power management strategies have been proposed for enterprise servers based on dynamic voltage and frequency scaling (DVFS), but those solutions cannot further reduce the energy consumption of a server when the server processor is already at the lowest DVFS level and the server utilization is still low (e.g., 5% or lower). To achieve improved energy efficiency, request batching can be conducted to group received requests into batches and put the processor into sleep between the batches. However, it is challenging to perform request batching on a virtualized server because different virtual machines on the same server may have different workload intensities. Hence, putting the shared processor into sleep may severely impact the performance of all the virtual machines. This paper proposes Virtual Batching, a novel request batching solution for virtualized servers with primarily light workloads. Our solution dynamically allocates CPU resources such that all the virtual machines can have approximately the same performance level relative to their allowed peak values. Based on this uniform level, our solution determines the time length for periodically batching incoming requests and putting the processor into sleep. When the workload intensity changes from light to moderate, request batching is automatically switched to DVFS to increase processor frequency for performance guarantees. Empirical results based on a hardware testbed and real trace files show that Virtual Batching can achieve the desired performance with more energy conservation than several well-designed baselines, e.g., 63% more, on average, than a solution based on DVFS only.

Parallel applications often rely on work stealing schedulers in combination with fine-grained tasking to achieve high performance and scalability. However, reducing the total energy consumption in the context of work stealing runtimes is still challenging, particularly when using asymmetric architectures with different types of CPU cores. A common approach for energy savings involves dynamic voltage and frequency scaling (DVFS) wherein throttling is carried out based on factors like task parallelism, stealing relations, and task criticality. This article makes the following observations: (i) leveraging DVFS on a per-task basis is impractical when using fine-grained tasking and in environments with cluster/chip-level DVFS; (ii) task moldability, wherein a single task can execute on multiple threads/cores via work-sharing, can help to reduce energy consumption; and (iii) mismatch between tasks and assigned resources (i.e., core type and number of cores) can detrimentally impact energy consumption. In this article, we propose EneRgy Aware SchedulEr (ERASE), an intra-application task scheduler on top of work stealing runtimes that aims to reduce the total energy consumption of parallel applications. It achieves energy savings by guiding scheduling decisions based on per-task energy consumption predictions of different resource configurations. In addition, ERASE is capable of adapting to both given static frequency settings and externally controlled DVFS. Overall, ERASE achieves up to 31% energy savings and improves performance by 44% on average, compared to the state-of-the-art DVFS-based schedulers.

Recent advancements in deep learning have significantly increased AI processors' energy consumption, which is becoming a critical factor limiting AI development. Dynamic Voltage and Frequency Scaling (DVFS) stands as a key method in power optimization. However, due to the latency of DVFS control in AI processors, previous works typically apply DVFS control at the granularity of a program's entire duration or sub-phases, rather than at the level of AI operators.

Dynamic Voltage and Frequency Scaling (DVFS) is widely used in today's mobile devices. Commonly adopted OS level DVFS policies usually operate with high sampling and adjustment frequency in order to compensate for the lack of information from applications. In this paper, we consider the application of video decoding and propose a method that enables DVFS at a coarse time granularity by taking advantage of application level semantics. Using machine learning, we build a prediction model for the choice of CPU frequency based on the estimated workload and the progress of execution. We show that with our method, the system is able to perform DVFS with a frequency of only around 1 Hz, abiding by the practical constraints imposed by existing operating systems, but still saves an average of 40.1% in energy consumption compared with the execution at nominal speed. Further, we argue that the law of diminishing returns applies if we increase the frequency at which DVFS operates, and thus it may be costly and impractical to perform application level DVFS at a very fine time granularity.

Modern data centers must provide performance assurance for complex system software such as multi-tier web applications. In addition, the power consumption of data centers needs to be minimized to reduce operating costs and avoid system overheating. Various power-efficient performance management strategies have been proposed based on dynamic voltage and frequency scaling (DVFS). Virtualization technologies have also made it possible to consolidate multiple virtual machines (VMs) onto a smaller number of active physical servers for even greater power savings, but at the cost of a higher overhead. This paper proposes a performance-controlled power optimization solution for virtualized data centers with multi-tier applications. While existing work relies on either DVFS or server consolidation in a separate manner, our solution utilizes both strategies for maximized power savings by integrating feedback control with optimization strategies. At the application level, a multi-input-multi-output controller is designed to achieve the desired performance for applications spanning multiple VMs, on a short time scale, by reallocating the CPU resources and DVFS. At the data center level, a power optimizer is proposed to incrementally consolidate VMs onto the most power-efficient servers on a longer time scale. Empirical results on a hardware testbed demonstrate that our solution can effectively achieve performance-assured power savings. Extensive simulation results, based on a trace file of 5,415 real servers, demonstrate the efficacy of our solution in large-scale data centers.

Dynamic Voltage and Frequency Scaling (DVFS) approach is proposed to control the power consumption in devices of different types like from a small mobile device to a huge server. This paper aims to study the effect of parallel execution of two benchmark applications, one the Stanford Single Source benchmarks (lightweight parallel code) and, Stanford Parallel Applications for Shared Memory (SPLASH-2) programs (heavy real-time data streaming parallel applications that run on multi -core clusters) on DVFS for dark silicon ameliorating. Both these benchmarks executed on a gem5 Full System simulator, booting a linaro based linux kernel. To get a holistic big picture of the power and thermal properties of systems that run on DVFS, in addition to the control feature present in gem 5, a power-estimation framework used for the evaluation of the efficiency of various DVFS policies, the MCPAT and Hotspot is also employed. Based on the execution of Stanford workloads DVFS model is analyzed in terms of memory footprint and on other critical processor performance metrics, like running time per core, bus latency, number of read, writes, access time, cache hit or miss. The gem5 is extended with full DVFS support by the addition of a framework in which easy power-model integration can be done.

DVFS-aware application classification to improve GPGPUs energy efficiency

Dynamic voltage and frequency scaling (DVFS) is a means to adjust the computing capacity and power consumption of computing systems to the application demands. DVFS is generally useful to provide a compromise between computing demands and power consumption, especially in the areas of resource-constrained computing systems. Many modern processors support some form of DVFS. In this article, we focus on the development of an execution framework that provides lightweight DVFS support for reactive stream processing systems (RSPS). RSPs are a common form of embedded control systems, operating in direct response to inputs from their environment. At the execution framework, we focus on support for many-core scheduling for parallel execution of concurrent programs. We provide a DVFS strategy for RSPs that is simple and lightweight, to be used for dynamic adaptation of the power consumption at runtime. The simplicity of the DVFS strategy became possible by the sole focus on the application domain of RSPs. The presented DVFS strategy does not require specific assumptions about the message arrival rate or the underlying scheduling method. While DVFS is a very active field, in contrast to most existing research, our approach works also for platforms like many-core processors, where the power settings typically cannot be controlled individually for each computational unit. We also support dynamic scheduling with variable workload. While many research results are provided with simulators, in our approach, we present a parallel execution framework with experiments conducted on real hardware, using the single-chip cloud computer many-core processor. The results of our experimental evaluation confirm that our simple DVFS strategy provides potential for significant energy saving on RSPs.

Energy-efficient resource allocation within clusters and data centers is important because of the growing cost of energy. We study the problem of energy-constrained dynamic allocation of tasks to a heterogeneous cluster computing environment. Our goal is to complete as many tasks by their individual deadlines and within the system energy constraint as possible given that task execution times are uncertain and the system is oversubscribed at times. We use Dynamic Voltage and Frequency Scaling (DVFS) to balance the energy consumption and execution time of each task. We design and evaluate (via simulation) a set of heuristics and filtering mechanisms for making allocations in our system. We show that the appropriate choice of filtering mechanisms improves performance more than the choice of heuristic (among the heuristics we tested).

Dynamic voltage and frequency scaling (DVFS) is heavily used for power management in real-time environments. Although the schemes leveraging DVFS provide significant power reduction, adverse effects on chip reliability are possible. Alternate increase and decrease in operating voltage and frequency leads to thermal cycling. Increasing transistor packing density leads to a larger range of possible operating temperatures, exacerbating the thermal cycling problem. Also, the chip reliability quantification process does not include and represent the effects of small scale thermal cycles. A good number of in-field chip failures are attributed to the consequences of these. Thus, it is imperative to include their effects into the processor voltage and frequency selection process. Our work develops an integrated processor thermal and performance management technique centered on novel polynomial time scheduling algorithms that lead to lowering of thermal cycles in soft real time environments. Our technique leverages application awareness and runtime monitoring for improving chip lifetime, while achieving considerable energy savings. We show that a significant reduction in thermal cycles and peaks is possible, leading to longer chip life expectations.

Personal portable devices such as DMB (digital multimedia broadcasting)s, PMP (portable multimedia player)s and PDA (portable digital assistant)s require long battery life without reducing their performance. Power consumption is one of important factors in ubiquitous environments. To reduce the dynamic power consumption, many researches have been conducted on the dynamic voltage and frequency scaling (DVFS). DVFS can reduce the power consumption proportionally to the square of the supply voltage. But processor operation under the critical speed increases the leakage current. Larger leakage current increases the static power consumption. This paper proposes a new power-aware scheduling algorithm that reduces the static and dynamic power consumption to use frequency scaling between two discrete voltage levels and under the critical speed while meeting the deadline of given applications. The simulation and experimental implementation show that the proposed scheduling algorithm results in up to 25% energy gains over traditional DVFS algorithms with two task scheduling policies.

Dynamic Voltage and Frequency Scaling (DVFS) is a method to save energy consumption of electronic devices and to protect them against overheating by automatic sensing and adaptation of their energy consumption. This can be accomplished either on the program instruction level for electronic devices or on the task or job level for server clusters. This paper models DVFS on the job level and through which Service Levels Objectives can be guaranteed with respect to prescribed mean or quantiles of service delays according to given Service Level Agreements (SLA) between user and service provider. The two parameters V (voltage) and f (frequency) cannot be changed independently of each other; typically only several combinations of V and f values are implemented in hardware for several power states. In this paper a novel analysis of operating DVFS is suggested for Server Clusters of Cloud Data Centers (CDC) under prescribed bounds of service level objectives which are defined by SLAs. The method is based on the theory of queuing models of the type GI/G/n for a server cluster to establish a relationship between SLA parameters and the power consumption and is performed for the example of the Intel Pentium M Processor with Enhanced SpeedStep Power Management. As result of this method precise bounds are provided for the load ranges of service request rates $\lambda$ for each power mode which guarantee minimum power consumption dependent on given SLA values and job arrival and service statistics. As the instantaneous load in a CDC can be highly volatile the current load level is usually monitored by periodic sensing which may result in a rather high frequency of DVFS range changes and corresponding overhead. For that reason an automated smoothing method is suggested which reduces the frequency of DVFS range changes significantly. This method is based on a Finite State Machine (FSM) with hysteresis levels.