Energy-Constrained Task Scheduling in Heterogeneous Distributed Systems

Energy-efficient VM opening algorithms for real-time workflows in heterogeneous clouds

NoC (Network-on-Chip) in recent times has been broadly used in majority of present multi-core (MC) processing environment (i.e., processor) (especially in cloud computing servers). Then, SoCs (System-on-Chips), as a scalable and flexible strategy to the widespread integration of higher number of element in the chips. Nonetheless, a main issue is reliable processing, performance efficiency and energy efficacy perquisite of BigData processing framework. This work assume self-aware MC architectures that autonomously adjust or optimize their performance to accommodate users quality of service (QoS) performance requirement, job execution performance, energy efficiency, and resource accessibility. Numerous researchers are concerned about the lack of energy conservation in cloud computing environment and hence numerous power efficient technologies are introduced by different researchers to protect environment by enormous amount of power dissipation and enhance the performance of the environment. However, these power efficient technologies requires enormous amount of interaction cost between inter-processors. Moreover, these technologies provides insufficient results and energy consumption of cloud computing devices cannot be reduced largely due to enormous amount of memory utilization, routing etc. For overcoming research challenges, this work present a novel performance and energy balanced scheduling (PEBS) approach in cloud environment based on Dynamic voltage and Frequency Scaling (DVFS) technique is proposed. Experiment outcome shows PEBS_DVFS model attains good trade-off between system performance and energy consumption in multicore cloud computing (CC) architectures when compared with existing model.

This paper presents a system level dynamic voltage and frequency scaling (DVFS) technique targeted toward non realtime applications running on a portable embedded system with multiple frequency-adjustable components. The key idea is to balance the frequency of processor core and memory. Some applications may be I/O bound, some may be CPU bound, and the others may be Memory bound. The proposed DVFS technique relies on pre-collected statistical information of different applications to calculate the expected workload for each coming time slice, and then, it adjusts the frequency of processor core, memory, and system bus to meet the timing constraints(with acceptable penalty) and achieves the maximum energy saving. The proposed technique has been tested on the PXA27x (XScale based) [8] embedded platform and the result was exciting, the processor energy saving can achieve up to 70% in memory bound applications, and the timing performance degradation was less than 5%. In CPU bound applications, the energy saving is relatively small, about 20~40%.

Reducing the power supply voltage is an effective technique to reduce dynamic power. Power shut-off (PSO) is also a well-known approach to reduce leakage power. In practice, one may employ multi-supply voltage or dynamic voltage and frequency scaling (DVFS) techniques accompanied with power gating and multi-depth sleep modes to reduce both of dynamic and leakage power consumption. As the voltage domains (power domains) and sleep modes (power modes) are increased dramatically, it is difficult to plan interface logics such as level shifters and isolation cells completely by manual for each power domain. In this paper, we present an interface planning methodology, and take a DVFS and power gating design with over 50 power domains and 80 power modes to demonstrate the verification challenges and our solutions. Besides, we propose a ldquoseamlessrdquo interface control circuit for PSO and DVFS designs. By using the circuit, the designs in the power on domain don't feel any data change when the opposite power domain is powered off.

Energy consumption has become a key metric for evaluating how good an embedded system is, alongside more performance metrics like respecting operation deadlines and speed of execution. Schedulability improvement is no longer the only metric by which optimality is judged. In fact, energy efficiency is becoming a preferred choice with a fundamental objective to optimize the system’s lifetime. In this work, we propose an optimal energy efficient scheduling algorithm for aperiodic real-time jobs to reduce CPU energy consumption. Specifically, we apply the concept of real-time process scheduling to a dynamic voltage and frequency scaling (DVFS) technique. We address a variant of earliest deadline first (EDF) scheduling algorithm called energy saving-dynamic voltage and frequency scaling (ES-DVFS) algorithm that is suited to unpredictable future energy production and irregular job arrivals. We prove that ES-DVFS cannot attain a total value greater than C/000000, where 000000 is the minimum speed of any job and C is the available energy capacity. We also investigate the implications of having in advance, information about the largest job size and the minimum speed used for the competitive factor of ES-DVFS. We show that such advance knowledge makes possible the design of semi-on-line algorithm, ES-DVFS**, that achieved a constant competitive factor of 0.5 which is proved as an optimal competitive factor. The experimental study demonstrates that substantial energy savings and highest percentage of feasible job sets can be obtained through our solution that combines EDF and DVFS optimally under the given aperiodic jobs and energy models.

Deep neural networks (DNNs) have been widely applied in diverse applications, but the problems of high latency and energy overhead are inevitable on resource-constrained devices. To address this challenge, most researchers focus on the dynamic voltage and frequency scaling (DVFS) technique to balance the latency and energy consumption by changing the computing frequency of processors. However, the adjustment of memory frequency is usually ignored and not fully utilized to achieve efficient DNN inference, which also plays a significant role in the inference time and energy consumption. In this paper, we first investigate the impact of joint memory frequency and computing frequency scaling on the inference time and energy consumption with a model-based and data-driven method. Then by combining with the fitting parameters of different DNN models, we give a preliminary analysis for the proposed model to see the effects of adjusting memory frequency and computing frequency simultaneously. Finally, simulation results in local inference and cooperative inference cases further validate the effectiveness of jointly scaling the memory frequency and computing frequency to reduce the energy consumption of devices.

As high quality real-time service demands on smart device applications are rapidly increasing, offloading the application task to the edge server to reduce total response time is emerging as a key issue. Meanwhile, smart devices are very sensitive to the energy consumption (to maximize the battery lifetime), where various energy consumption schemes have been attempted to minimize the power profile, especially for computationally heavy tasks. In this paper, an energy consumption minimization scheme that adjusts both the offloading ratio and CPU operating frequency of the device based on a Dynamic Voltage and Frequency Scaling (DVFS) technique under delay constraint is proposed. Simulation results show that the proposed scheme minimizes the energy consumption of the device while satisfying the delay requirement.

CPU-GPU accelerator based heterogeneous cloud computing systems can give enhanced energy efficiency and performance. Both energy efficiency and performance parameters are the vital factors in achieving High Performance Computing (HPC). To completely understand the strength of heterogeneous cloud computing architectures, software must efficiently use CPU-GPU processing and their power conserves capability. Dynamic Voltage and Frequency Scaling (DVFS) technique can be used to enable power conserving capabilities of CPU-GPU core architectures. Therefore, to distribute task load between host CPUs and GPU accelerators and reduce energy consumption, here, we have introduced a Heterogeneous Dynamic Scheduling Minimized Makespan (HDSMM) using CPU-GPU cores for heterogeneous cloud computing devices. Here, DVFS technique is distributed into CPU-DVFS and GPU-DVFS, for efficient resource utilization and to exploit power conserving features. Our proposed HDSMM model presents precise modeling for performance and energy efficiency distribution and finest frequency to achieve either best performance or lowest power consumption. Experimental results verify the superiority of our proposed HDSMM model in terms of energy consumption, average execution time and average power for scientific benchmark Montage.

The use of power management techniques is mandatory in embedded devices, which must provide high performance with low energy consumption. Due to the high variability present in the applications workload executed by these devices, this management should be executed dynamically. The use of traditional dynamic voltage and frequency scaling (DVFS) techniques proved to be useful in several scenarios to save energy. Nonetheless, due to technology scaling that limits the voltage variation and slow response of the DVFS schemes, the use of such technique may become inadequate. As alternative, the use of dynamic frequency scaling (DFS) may provide a good trade-off between power savings and power overhead. This paper proposes a distributed DFS scheme for NoC-based MPSoCs. Both NoC and PEs have an individual controlling scheme. The DFS scheme for PEs takes into account its computation and communication load to dynamically change the operating frequency. In the NoC, the DFS controller uses packet information to decide the router operating frequency. Real and synthetic applications were used to evaluate the proposed scheme. Results show that the number of executed instructions is reduced up to 41%, with an execution time overhead up to 18%. The power dissipation is reduced in PEs up to 26% and in the NoC up to 76%.

As processor count in MPSoCs increases, the use of NoCs becomes relevant, if not mandatory. However, power and energy restrictions, especially in mobile applications, may render the design of NoC-based MPSoCs over-constrained. The use of traditional dynamic voltage and frequency scaling (DVFS) techniques proved useful in several scenarios to save energy/power, but it presents scaling problems and slow response times. This work proposes a self-adaptable distributed dynamic frequency scaling (DFS) scheme for NoC-based MPSoCs. It takes into account the communication load and the utilization level of each processor to dynamically change its operating frequency. Frequency change decisions and clock generation are executed locally to each processor. Clock generation is simple, based on clock gating of a single global clock. The overhead of the scheme is minimum, the range of generated clocks is wide, and the response time is negligible. Experimental results with synthetic applications shows that the proposed scheme has an average execution time overhead below 7%, and may lead to considerable power and energy savings, since it allows an average reduction of 27% on the total number of executed instructions. Evaluating the proposed method with a real application, the execution time overhead reached 13%, while the total number of executed instructions was reduced by 64%.

In this paper, we propose a novel accuracy-reconfigurable stochastic computing (ARSC) framework for dynamic reliability and power management. Different than the existing stochastic computing works, where the accuracy versus power/energy trade-off is carried out in the design time, the new ARSC design can change accuracy or bit-width of the data in the run-time so that it can accommodate the long-term aging effects by slowing the system clock frequency at the cost of accuracy while maintaining the throughput of the computing. We validate the ARSC concept on a discrete cosine transformation (DCT) and inverse DCT designs for image compressing/decompressing applications, which are implemented on Xilinx Spartan-6 family XC6SLX45 platform. Experimental results show that the new design can easily mitigate the long-term aging induced effects by accuracy trade-off while maintaining the throughput of the whole computing process using simple frequency scaling. We further show that one-bit precision loss for the input data, which translated to 3.44dB of the accuracy loss in term of Peak Signal to Noise Ratio (PSNR) for images, we can sufficiently compensate the NBTI induced aging effects in 10 years while maintaining the pre-aging computing throughput of 7.19 frames per second. At the same time, we can save 74% power consumption by 10.67dB of accuracy loss. The proposed ARSC computing framework also allows much aggressive frequency scaling, which can lead to order of magnitude power savings compared to the traditional dynamic voltage and frequency scaling (DVFS) techniques.

In this paper, we address the problem of energy reduction when scheduling streaming applications with throughput constraints on homogeneous multiprocessor systems with voltage and frequency scaling capability. We propose a novel periodic scheduling framework which allows streaming applications to switch their execution periodically between a few energy-efficient schedules at run-time in order to meet a throughput constraint at long run. Using such periodic switching, we can benefit from adopting Dynamic Voltage and Frequency Scaling (DVFS) techniques to exploit available static slack time in the schedule of an application efficiently. The experimental results, on a set of real-life streaming applications, show that our novel scheduling approach can achieve up to 68% energy reduction depending on the application and the throughput constraint compared to related approaches.

Energy efficiency is a major concern in modern high-performance computing system design. In the past few years, there has been mounting evidence that power usage limits system scale and computing density, and thus, ultimately system performance. However, despite the impact of power and energy on the computer systems community, few studies provide insight to where and how power is consumed on high-performance systems and applications. In previous work, we designed a framework called PowerPack that was the first tool to isolate the power consumption of devices including disks, memory, NICs, and processors in a high-performance cluster and correlate these measurements to application functions. In this work, we extend our framework to support systems with multicore, multiprocessor-based nodes, and then provide in-depth analyses of the energy consumption of parallel applications on clusters of these systems. These analyses include the impacts of chip multiprocessing on power and energy efficiency, and its interaction with application executions. In addition, we use PowerPack to study the power dynamics and energy efficiencies of dynamic voltage and frequency scaling (DVFS) techniques on clusters. Our experiments reveal conclusively how intelligent DVFS scheduling can enhance system energy efficiency while maintaining performance.

Mobile cloud computing (MCC) as an emerging and prospective computing paradigm, can significantly enhance computation capability and save energy of smart mobile devices (SMDs) by offloading computation-intensive tasks from resource-constrained SMDs onto the resource-rich cloud. However, how to achieve energy-efficient computation offloading under the hard constraint for application completion time remains a challenge issue. To address such a challenge, in this paper, we provide an energy-efficient dynamic offloading and resource scheduling (eDors) policy to reduce energy consumption and shorten application completion time. We first formulate the eDors problem into the energy-efficiency cost (EEC) minimization problem while satisfying the task-dependency requirements and the completion time deadline constraint. To solve the optimization problem, we then propose a distributed eDors algorithm consisting of three subalgorithms of computation offloading selection, clock frequency control and transmission power allocation. More importantly, we find that the computation offloading selection depends on not only the computing workload of a task, but also the maximum completion time of its immediate predecessors and the clock frequency and transmission power of the mobile device. Finally, our experimental results in a real testbed demonstrate that the eDors algorithm can effectively reduce the EEC by optimally adjusting the CPU clock frequency of SMDs based on the dynamic voltage and frequency scaling (DVFS) technique in local computing, and adapting the transmission power for the wireless channel conditions in cloud computing.

The negative effects of the Dynamic Voltage and Frequency Scaling (DVFS) technique on the system reliability has recently promoted the research on reliability-aware power management (RAPM). RAPM aims at reducing the system energy consumption while preserving the system's reliability. In this paper, we study the RAPM problem for parallel realtime applications for shared memory multiprocessor systems in the presence of precedence constraints. We show that this problem is NP-hard. Depending on how recoveries are scheduled and utilized by a subset of selected tasks, we investigate both individual-recovery and shared-recovery based RAPM heuristics. Online RAPM schemes that exploit dynamic slack generated at runtime are also considered. The proposed schemes are evaluated through extensive simulations. The results show that all schemes can preserve system reliability under all settings. For modest system loads, similar energy savings are obtained by all static schemes. However, when the system load is low, the shared-recovery based schemes need coordinated recovery operations on all processors and thus save less energy. Moreover, by reclaiming dynamic slack, the online schemes yield better energy savings.