Energy Efficient Memory Architecture for High Performance and Low Power Applications Under Sub-threshold Regime

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Abstract In recent years, digital VLSI circuits operating under sub-threshold operation have gained a lot of attention due to the rapid growth in technology from low to high performance applications. In addition to that, performance is improved by device dimensions and circuit operations under threshold regime. This leads to promising technology for future memory designs for ultra-low power applications. On the other hand, there is an issue of static or leakage current that leads to a reduction of performance. Novelty of research in the paper described the design and implementation of energy efficient SRAM designs such as Saturated NMOS SRAM, Schmitt trigger-based SRAM’s working under sub-threshold for ultra-low power applications by measuring leakage power. Both logic, circuit and architecture level designs have extensively analyzed to evaluate the performance and functionality of SRAM designs. Comparative analysis is made on the basis of read, write performance, SNM, along with the functionality of static, dynamic characteristics.KeywordsSaturated NMOSSchmitt trigger SRAMSub-thresholdStatic currentLow power