Energy-optimized ternary full adder based on capacitive threshold logic and multi-threshold CNTFETs applicable in digital signal processing

The main drawback of Capacitive Threshold Logic (CTL) gates relates to the threshold valid programming. Because each gate may require a different reference voltage to set its threshold it is practically impossible to use this approach to build circuits with more than a couple of gates. In this paper we propose a new scheme, the Capacitor Programmable CTL (CP-CTL), which alleviate the CTL gate programming issue. The CP-CTL implementation of a 32-bit adder as also presented.

In this paper the authors present the main aspects of the Capacitive Threshold Logic (CTL) implementation. Several unique design problems typical to CTL design are presented using a design perspective. We also address the CTL implementation of /spl delta/-bit serial binary addition, performing a qualitative analysis of different implementation dependent approaches.

Compact low depth carry look-ahead circuits using rail-to-rail capacitive threshold logic are proposed. Experimental results of a fabricated test chip from MOSIS in 0.5 mum CMOS technology are presented that validate the proposed circuits operating with a single supply as low as 1.8 V.

Today, DAW (Digital Audio Workstation) software lies at the heart of music production and has become an indispensable part of the industry. With the advancement of technology, music production is no longer confined to large studios but has also become accessible to individual users. Now, recording, mixing, and mastering processes can be carried out in a home environment using computer-based systems, without the need for expensive equipment. This fully digital workflow is referred to as "in-the-box" production. Technological developments have enabled individuals to produce music at a professional level in home studios, leading to the emergence of digital alternatives to analog devices. Digital processors have begun to replace analog equipment due to their cost-effectiveness and practicality. This study examines the differences between digital signal processors and analog devices in terms of usage, application areas, and sound processing methods. The research aims to compare digital and analog signal processors, particularly focusing on their processing methods, speed, flexibility, quality, and impact on sound. Based on the findings, it is concluded that digital signal processors, which are increasingly replacing analog processors in the music industry, do not possess the same characteristics as their analog counterparts.

A new modular architecture is presented for the realization of high-speed binary sorting engines, based on efficient rank ordering. Capacitive Threshold Logic (CTL) gates are utilized for the implementation of the multi-input programmable majority (voting) functions required in the architecture. The overall complexity of the proposed bit-serial architecture increases linearly with the number of input vectors to be sorted (window size=m) and with the bit-length of the input vectors (word size=n), and the sorter architecture can be easily expanded to accommodate large vector sets. Detailed simulations indicate that the sorter structure can operate at sampling clock rates of up to 50 MHz, where the throughput is boosted by fine-grain pipelining. It is demonstrated that the proposed sorting engine is capable of producing a fully sorted output vector set in (m+n-1) clock cycles, i.e., in linear time.

A new modular architecture is presented for the realization of high-speed binary sorting engines, based on efficient rank ordering. Capacitive Threshold Logic (CTL) gates are utilized for the implementation of the multi-input programmable majority (voting) functions required in the architecture. The overall complexity of the proposed bit-serial architecture increases linearly with the number of input vectors to be sorted (window size=m) and with the bit-length of the input vectors (word size=n), and the sorter architecture can be easily expanded to accommodate large vector sets. It is demonstrated that the proposed sorting engine is capable of producing a fully sorted output vector set in (m+n-1) clock cycles, i.e., in linear time.

The development of modern technologies has fundamentally transformed the field of radar signal and data processing. With the use of advanced algorithms and computational power, radars are now capable of extracting crucial information from received signals, facilitating improved target identification and tracking. This article presents some of the advanced technologies employed in radar signal and data processing and their impact on adaptability of radar systems. It traces the evolution of radar technology from old systems to the present, emphasizing the benefits of adaptive radar signal processing, which includes algorithms such as adaptive beamforming, Space-Time Adaptive Processing, and the integration of Machine Learning and Artificial Intelligence. In conclusion, challenges, and future prospects in the field of radar systems are discussed, with a focus on the potential integration of Artificial Intelligence methods, Cognitive radars, and Multiple Input Multiple Output technologies. Despite technical obstacles, opportunities emerge to enhance the performance of radar systems and achieve new levels of efficiency.

The rapid increase in digital signal processing (DSP) applications has generated a strong demand for electrical engineers with DSP backgrounds; however, the gap between industry needs and university curricula still exists. To answer this challenge, a sequence of innovative DSP courses that emphasize hands-on experiments and practical applications were developed for continuing education in electrical and computer engineering. These courses are taught in the evening for night-school students having at least three years of work experience. These courses enable students to experiment with sophisticated DSP applications to augment the theoretical, conceptual, and analytical materials provided in traditional DSP courses. The inclusion of both software and hardware developments allows students to undertake a wide range of DSP projects for real-world applications. Assessment data concludes that the digital signal processor fundamentals course can increase learning interest and overcome the prerequisite problem of DSP laboratory experiments. This paper also briefly introduces representative examples of some challenging DSP applications.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

Energy consumption in Digital Signal Processing (DSP) application is a vital parameter of consideration. Mostly DSP applications deplete power. Battery constraint is important in many mobiles, processors, and sensor-related devices. The major critical operations in DSP architecture are multiplication and addition. Multiplication process is performed using repetitive addition. Hence, adder is the basic component used in digital signal processor. DSP architecture is proposed with the energy-efficient goal. Traditional carry select adder contains ripple carry adder block is replaced by parallel prefix adder. By replacing that block and introducing folded tree, we can reduce power used by DSP processors. This architecture can be used in all power constrained DSP applications. In the existing system, folded tree is used in architecture to reduce the number of processing elements, and they used carry look-ahead adder to perform the internal processing element operations. In the proposed system, carry look-ahead adder is replaced by LFA and PA to harness the energy depleted in an application (e.g., DSP application). Power consumption is reduced by 12–15% as compared with the existing algorithms using Cyclone III (EP3C16F484C6).

A lot of modern ultrasonic measurement (UM) applications use digital signal processing (DSP). In many cases DSP comprises a significant part of system hardware and cost, also it sets certain restrictions on measurement speed and signal-to-noise ratio. This paper deals with the influence of the DSP into signal-to-noise ratio and its relevant characteristicsIt presents a concept of DSP exploration in applications. According to this concept the integrated model UM application - DSP architecture is used to select the rational DSP following the application requirements. The exploration is illustrated with the correlational time delay estimation task. The exploration method was suggested and applied in two scientific projects that have done by Ultrasound Research Center and DSP Laboratory at Kaunas University of Technology. During these projects the ultrasonic vision system for mobile robot (project INCO-COPERNICUS No. ERB IC15-CT96-0726) and high precision ultrasonic gas flowmeter have been designed. In both cases signal processing was necessary and the DSP design presented quite serious problem. The model is implemented in software and provides high flexibility. It can be modified for different DSP methods and signals, therefore, it is applicable for the design of various systems.

Comparison of milk-clotting activity measurement using the Berridge's operator-based approach and a proposed digital method

The surge in interest regarding the next generation of optical fiber transmission has stimulated the development of digital signal processing (DSP) schemes that are highly cost-effective with both high performance and low complexity. As benchmarks for nonlinear compensation methods, however, traditional DSP designed with block-by-block modules for linear compensations, could exhibit residual linear effects after compensation, limiting the nonlinear compensation performance. Here we propose a high-efficient design thought for DSP based on the learnable perspectivity, called learnable DSP (LDSP). LDSP reuses the traditional DSP modules, regarding the whole DSP as a deep learning framework and optimizing the DSP parameters adaptively based on backpropagation algorithm from a global scale. This method not only establishes new standards in linear DSP performance but also serves as a critical benchmark for nonlinear DSP designs. In comparison to traditional DSP with hyperparameter optimization, a notable enhancement of approximately 1.21 dB in the Q factor for 400 Gb/s signal after 1600 km fiber transmission is experimentally demonstrated by combining LDSP and perturbation-based nonlinear compensation algorithm. Benefiting from the learnable model, LDSP can learn the best configuration adaptively with low complexity, reducing dependence on initial parameters. The proposed approach implements a symbol-rate DSP with a small bit error rate (BER) cost in exchange for a 48% complexity reduction compared to the conventional 2 samples/symbol processing. We believe that LDSP represents a new and highly efficient paradigm for DSP design, which is poised to attract considerable attention across various domains of optical communications.

In conventional buck-boost converters, the output voltage is inverted. Hardware circuitry or microcontrollers are used to trigger a switch in the converter. In the proposed study, a non inverting buck-boost converter is implemented for PV system. The Pulse width modulation (PWM) signals for two MOSFETS in the converter are generated by DSP TMS 320 2808. Depending on the solar panel input, buck-boost converter charges the battery. The DC loads are driven from the battery. The load voltage and load current are sensed and compared with the reference voltage. Hardware circuitry or microcontroller is less accurate and using these systems the solar energy cannot be efficiently converted into electrical energy. In industry and commercial applications Digital Signal Processor (DSP) is used for automation. The same DSP can be used to generate PWM signals so as to get maximum electrical energy from solar energy. The DSP is more accurate and this works in real-time scenarios. The efficient utilization of resources such as DSP is achieved in the proposed study as the same DSP is used for generating PWM signal. In the proposed study, PWM signals are generated from DSP depending on load voltage and load current. The proposed work is better as compared to existing systems in terms of line and load regulation, efficiency, accuracy and speed as validated by experimental results.

Programmable logic offers an alternative solution for the computationally-intensive functions found in digital signal processing (DSP). Programmable logic can provide increased DSP system performance at reduced system cost. Programmable logic combines the flexibility of a general purpose DSP plus the speed, density, and low cost of an ASIC implementation. In some applications, programmable logic replaces the DSP processor entirely. In others, programmable logic works in conjunction with the DSP processor, offloading the computationally-intensive function and freeing the processor for other functions. This paper describes an alternative to traditional, general-purpose DSP processors. Programmable logic can implement functions beyond the capabilities of today's DSP processors. Field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs) potentially provide performance increases of an order of magnitude over traditional DSPs with the same flexibility.