Enhanced partitioned scheduling of Mixed-Criticality Systems on multicore platforms

The cluster-based technique is gaining focus for scheduling tasks of mixed-criticality (MC) real-time multicore systems. In this technique, the cores of the MC system are distributed in groups known as clusters. When all cores are distributed in clusters, the tasks are partitioned into clusters, which are scheduled on the cores within each cluster using a global approach. In this study, a cluster-based technique is adopted for scheduling tasks of real-time mixed-criticality systems (MCS). The Decreasing Criticality Decreasing Utilization with the worst-fit (DCDU-WF) technique is used for partitioning of tasks to clusters, whereas a novel mixed-criticality cluster-based boundary fair (MC-Bfair) scheduling approach is used for scheduling tasks on cores within clusters. The MC-Bfair scheduling algorithm reduces the number context switches and migration of tasks, which minimizes the overhead of mixed-criticality tasks. The migration and context switch overhead time is added at the time of each migration and context switch respectively for a task. In low critical mode, the low mode context switch and migration overhead time is added to task execution time, while the high mode overhead time of migration and context switch is added to the execution time of a task in high critical mode. The results obtained from experiments show the better schedulablity performance of proposed cluster-based technique as compared to cluster-based fixed priority (CB-FP), MC-EKG-VD-1, global and partitioned scheduling techniques e.g., for target utilization U=0.6, the proposed technique schedule 66.7% task sets while MC-EKG-VD-1, CB-FP, partitioned and global techniques schedule 50%, 33.3%, 16.7% and 0% task sets respectively.

In the field of real-time systems, component-based models for mixed criticality systems (MCS) on multicore platform are gaining significant attention of the researchers from the recent past. The concept of mixed-criticality is firstly applied on single core systems but after gaining attention, it evolved to multicore platform. Initially, the tasks of MCS executes in low mode however if a task having high criticality does not its scheduling requirements complete its low mode, then the system switch to high mode. In high mode, only high critical tasks executes its high mode scheduling requirements, while all low tasks are discarded from further execution. In the realm of MCS, the component-based model have high importance and has been used in large and complex real-time systems. In component-based model, the component of a system is splatted into multiple components. In this study, a new component-based scheduling approach is proposed for multicore MCS. In the multicore mixed-criticality compositional framework, special emphasis is given on deriving the supply bound function, which represents available core supply, and the demand bound function, which indicates the requirements of resources for scheduling. A mixed-criticality multicore compositional framework (MMCF) is introduced for component-based MCS having tightened deadline. For the proposed strategy, a schedulability analysis is conducted, ensuring that the system can be scheduled only if the supply bound function is equal to or less than the demand bound function. On a 4-core platform, the scheduleability for the three scheduling strategies i.e. MMCF, MC-Partition, and Global are shown at different utilization levels of resource. 100% schedulability is shown by the proposed MMCF, MC-Partition, and global techniques for target utilizations of 0.7, 0.5, and 0.4, respectively. For a given utilization U=0.6, the proposed MMCF approach shows 100 % schedulability, while the MC-partition and global approaches show 90% and 20% schedulabilities respectively. It shows that the proposed MMCF approach schedules 10% and 80% more task sets than the MC-partition and global approaches respectively. The experimental results reveal that the proposed MMCF approach offers better schedulability than the other two approaches.

A common trend in real-time embedded systems is to integrate multiple applications on a single platform. Such systems are known as mixed-criticality (MC) systems when the applications are characterized by different criticality levels. Nowadays, multicore platforms are promoted due to cost and performance benefits. However, certification of multicore MC systems is challenging as concurrently executed applications of different criticalities may block each other when accessing shared platform resources. Most of the existing research on multicore MC scheduling ignores the effects of resource sharing on the response times of applications. Recently, a MC scheduling strategy was proposed, which explicitly accounts for these effects. This paper discusses how to combine this policy with an optimization method for the partitioning of tasks to cores as well as the static mapping of memory blocks, i.e., task data and communication buffers, to the banks of a shared memory architecture. Optimization is performed at design time targeting at minimizing the worst-case response times of tasks and achieving efficient resource utilization. The proposed optimization method is evaluated using an industrial application.

Multi-core architectures have grown to be a popular choice for deploying Mixed Criticality Systems (MCS). The focus of research in MCS has been to provide timing assurances for jobs with different criticality levels. Due to their significant processing demands and energy-aware/constrained nature, energy conservation in these systems is becoming mandatory. This article presents, mcDVFS, an energy management technique based on Dynamic-Voltage-and-Frequency-Scaling for multi-core MCS. mcDVFS achieves significant energy reduction while maintaining timing guarantees. It also prioritizes quality of service whenever feasible. Extensive experimental simulations show energy savings of ≈ 52% and 34% when compared to EDF-VD and EDF-VD with QoS.

Mixed-Criticality Systems (MCS) reconcile safetycritical requirements with multi-core architectures, by offering spatial and temporal isolation while preserving other extrafunctional properties such as optimised energy consumption or minimised latencies. MCS designers struggle to manually balance the offered functionalities with pertinent implementation choices in order to ensure that the system eventually meets all constraints. Existing attempts to further automate this process focus on specific concerns, and fail to account for variation in system functionalities. Our contribution is to integrate product-lines that capture functional variations with evolutionary optimisation to explore possible implementations and their impact on extrafunctional properties. Our solution is a model-driven process (and a tool prototype) to automatically select functionally different products that balance well the various concerns of interest. We illustrate how this process applies to the construction of wind turbines. Moving toward product-lines eventually contributes to reduce high development costs and the long time to market associated with MCS.

The shift towards multi-core platforms has become inevitable from an industry perspective, therefore proper techniques are needed to deal with challenges related to this migration from single core architectures to a multi-core architecture. One of the main concerns for system developers in this context is the migration of legacy real-time systems to multi-core architectures. To address this concern and to simplify the migration, independently-developed subsystems are abstracted with an interface, such that when working with multiple independently-developed subsystems to be integrated on a shared platform, one does not need to be aware of information or policies used in other subsystems in order to determine subsystem-level schedulability. Instead schedulability can be checked through their interfaces at the time of integration on a shared multi-core architecture. In this paper we propose a solution for investigating the system schedulability via providing interfaces for independently-developed subsystems where some of them are distributed over more than one processor and may share resources.

Multi-core computer architectures are on the forefront in consumer electronics and adaptation in safety-critical applications such as avionics could be beneficial due to their potential increased performance. Yet, there are challenges to deploy cutting edge multi-core architectures for safety-critical applications. New computing architectures are more integrated and optimized for average cases. On the other side, safety-critical applications need to be designed for the worst case. For example, the impact of integrating critical applications is not fully understood yet, especially with respect to execution times of critical paths. This paper proposes and argues an approach to quantify the impact of integration of multiple independent applications onto multi-core platforms and evaluates the approach on a specific potential future avionics computing platform. Evaluation results focusing on execution estimates show that multi-core computers may be used for safety-critical applications, but the worst-case execution time (WCET) can be multiple times slower than the same application running on a single core without other cores running interfering applications. The actual factor is very dependent on the application's use of shared resources like memory.

SUMMARYThe objective of this paper is to analyze the dynamic scheduling of dense linear algebra algorithms on shared‐memory, multicore architectures. Current numerical libraries (e.g., linear algebra package) show clear limitations on such emerging systems mainly because of their coarse granularity tasks. Thus, many numerical algorithms need to be redesigned to better fit the architectural design of the multicore platform. The parallel linear algebra for scalable multicore architectures library developed at the University of Tennessee tackles this challenge by using tile algorithms to achieve a finer task granularity. These tile algorithms can then be represented by directed acyclic graphs, where nodes are the tasks and edges are the dependencies between the tasks. The paramount key to achieve high performance is to implement a runtime environment to efficiently schedule the execution of the directed acyclic graph across the multicore platform. This paper studies the impact on the overall performance of some parameters, both at the level of the scheduler (e.g., window size and locality) and the algorithms (e.g., left‐looking and right‐looking variants). We conclude that some commonly accepted rules for dense linear algebra algorithms may need to be revisited. Copyright © 2011 John Wiley & Sons, Ltd.

Locking cache lines in hard real-time systems is a common means of achieving predictability of cache access behavior and tightening as well as reducing worst case execution time, especially in a multitasking environment. However, cache locking poses a challenge for multi-core hard real-time systems since theoretically optimal scheduling techniques on multi-core architectures assume zero cost for task migration. Tasks with locked cache lines need to proactively migrate these lines before the next invocation of the task. Otherwise, cache locking on multi-core architectures becomes useless as predictability is compromised. This paper proposes hardware-based push-assisted cache migration as a means to retain locks on cache lines across migrations. We extend the push-assisted migration model with several cache migration techniques to efficiently retain locked cache lines on a bus-based chip multi-processor architecture. We also provide deterministic migration delay bounds that help the scheduler decide which migration technique(s) to utilize to relocate a single or multiple tasks. This information also allows the scheduler to determine feasibility of task migrations, which is critical for the safety of any hard real-time system. Such proactive migration of locked cache lines in multi-cores is unprecedented to our knowledge.

Locking cache lines in hard real-time systems is a common means of achieving predictability of cache access behavior and tightening as well as reducing worst case execution time, especially in a multitasking environment. However, cache locking poses a challenge for multi-core hard real-time systems since theoretically optimal scheduling techniques on multi-core architectures assume zero cost for task migration. Tasks with locked cache lines need to proactively migrate these lines before the next invocation of the task. Otherwise, cache locking on multi-core architectures becomes useless as predictability is compromised. This paper proposes hardware-based push-assisted cache migration as a means to retain locks on cache lines across migrations. We extend the push-assisted migration model with several cache migration techniques to efficiently retain locked cache lines on a bus-based chip multi-processor architecture. We also provide deterministic migration delay bounds that help the scheduler decide which migration technique(s) to utilize to relocate a single or multiple tasks. This information also allows the scheduler to determine feasibility of task migrations, which is critical for the safety of any hard real-time system. Such proactive migration of locked cache lines in multi-cores is unprecedented to our knowledge.

Mixing tasks of different criticality levels on the same processor has become common in modern embedded systems. Scheduling these complex systems on multicore processors is difficult, especially when targeting high utilization. The overload in mixed criticality systems is one of the important problems that faces system designers and may force them to lower the cores utilization to avoid this risky problem. If a fully utilized system is overloaded and no solution is applied, many of coming jobs will miss their deadlines and the system may stay overloaded all the time and never return back to its normal behavior. So, the overload must be transient and the system should guarantee that it can return back its normal behavior shortly after overload happens. In this paper, we present a kernel-based solution for the overload in mixed criticality systems using virtual time. A virtual timer delays the release time and deadlines of tasks in an overload state for a short time to guarantee that it can return back as quickly as possible to its normal behavior. The proposed solution avoids using any user space invocation, as it detects the overload and recovers from it completely inside the kernel space. Our experiments show that the time to recover from overload once it happens is decreased using our proposed technique.

As real-time embedded systems integrate more and more functionality, they are demanding increasing amounts of computational power that can only be met by deploying them on powerful and scalable multicore architectures. The use of multicore architectures with on-chip memory hierarchies and shared communication infrastructure in the context of real-time systems poses several challenges for task scheduling. Semi-partitioned scheduling algorithms form a middle ground between the two extreme approaches, namely global and partitioned scheduling. In such an algorithm, a subset of tasks are partitioned onto cores and the remaining tasks are allowed to migrate in a pre-specified manner. By making most tasks non-migrating (partitioned), runtime migration overhead is minimized. On the other hand, by allowing some tasks to migrate among cores, schedulability is improved. In this paper, we present a predictable semi-partitioned scheduling algorithm for independent hard-real-time sporadic tasks executing on homogeneous multicore platforms using cache locking and locked cache migration. As part of the semi-partitioned scheduling algorithm, we propose two different task ordering schemes and two different schemes for the initial partitioning phase. Simulation results demonstrate the effectiveness of the proposed schemes in comparison to existing state-of-the-art techniques.

MOSART project addresses two main challenges of prevailing architectures: (1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; (2) The difficulties in programming heterogeneous, multi-core platforms MOSART aims to overcome these through a multi-core architecture with distributed memory organization, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimized and customized together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: (1) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure; (2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.KeywordsAbstract Data TypeWorkload ModelPower Management SystemMemory AllocatorJPEG EncoderThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The integration of mixed-critical tasks into a platform is an increasingly important trend in the design of real-time systems due to its efficient resource usage. With a growing variety of activation patterns considered in real-time systems, some of them capture arbitrary activation patterns. As a consequence, the existing scheduling approaches in mixed-criticality systems (MCs), which assume the sporadic tasks with implicit deadlines, have sometimes become inapplicable or are ineffective. In this paper, we extend the sporadically activated task model to the arbitrarily activated task model in MCs with the preemptive fixed-task-priority schedule. By using the event arrival curve to model task activations, we present the necessary and sufficient schedulability tests that are based on the well-established results from Real-Time Calculus. We propose to use the busy-window analysis to do the sufficient test because it has been shown to be tighter than the sufficient test of using Real-Time Calculus. According to our experimental results, for sporadic task sets, our proposed test can achieve the same performance as the state-of-the-art schedulability test. However, compared with the previous schedulability analysis of preemptive fixed-task-priority, our approaches can handle more general tasks with blocking, jitter, and arbitrary deadlines.

Formal analysis of feature degradation in fault-tolerant automotive systems