Enhanced superscalar hardware

There is wide agreement that one of the most important impediments to the performance of current and future pipelined superscalar processors is the presence of conditional branches in the instruction stream. Speculative execution seems to be one solution of choice to the branch problem, but speculative work is discarded if a branch is mispredicted. Therefore, we need a very accurate branch predictor; 95% accuracy is not good enough. This paper proposes branch classification to help improve the accuracy of branch predictors. Branch classification allows an individual branch instruction to be associated with the branch predictor best suited to predict its direction. Using this approach, a hybrid branch predictor can be constructed such that each component branch predictor predicts those branches for which it is best suited. This paper suggests one classification scheme, analyzes several branch predictors, and proposes a hybrid branch predictor that achieves higher prediction accuracy than any branch predictor previously reported in the literature.

The schedulability analysis of real-time embedded systems requires worst case execution time (WCET) analysis for the individual tasks. Bounding WCET involves not only language-level program path analysis, but also modeling the performance impact of complex micro-architectural features present in modern processors. In this paper, we statically analyze the execution time of embedded software on processors with speculative execution. The speculation of conditional branch outcomes (branch prediction) significantly improves a program's execution time. Thus, accurate modeling of control speculation is important for calculating tight WCET estimates. We present a parameterized framework to model the different branch prediction schemes. We further consider the complex interaction between speculative execution and instruction cache performance, that is, the fact that speculatively executed blocks can generate additional cache hits/misses. We extend our modeling to capture this effect of branch prediction on cache performance. Starting with the control flow graph of a program, our technique uses integer linear programming to estimate the program's WCET. The accuracy of our method is demonstrated by tight estimates obtained on realistic benchmarks.

The need for modern processors is based on fast and precise branch predictors to improve the execution of instructions in the pipeline. In a parallel processor, the pipeline cannot execute the conditional instructions with the next clock cycle, leading to a pipeline stall. To address this issue, this paper suggests a variety of branch prediction techniques for improving the execution speed of conditional instructions. Firstly, a simple branch prediction and a dynamic branch prediction are applied to the trace files using saturating counters. Among these two, dynamic branch prediction provides better results by enhancing the accuracy rate of 2.01% than the static branch prediction. Further, the perceptron branch predictor predicts the implementation by using a table of perceptron and train function. This prediction scheme reduces the difficulties in dynamic branch predictor schemes such as reduces the complexity in history length table and improves the accuracy rate by 5.36%. For accuracy, a novel model based on global perceptron branch predictor is developed, which uses both global and per branch information. Trace-driven simulations have been performed by varying the range of hardware budget, traces file size, and the length of history register to increase the accuracy rate of each branch prediction technique. The obtained results suggest that the proposed global perceptron branch predictor provides an increased accuracy rate of 10.47% at 4 kb hardware budget and 8.06% at 4-bit history length than the perceptron branch predictor.

Pipeline stalls due to conditional branches represent one of the most significant impediments to realizing the performance potential of deeply pipelined, superscalar processors. Many branch predictors have been proposed to help alleviate this problem, including the Two-Level Adaptive Branch Predictor, and more recently, two-component hybrid branch predictors.In a less idealized environment, such as a time-shared system, code of interest involves context switches. Context switches, even at fairly large intervals, can seriously degrade the performance of many of the most accurate branch prediction schemes. In this paper, we introduce a new hybrid branch predictor and show that it is more accurate (for a given cost) than any previously published scheme, especially if the branch histories are periodically flushed due to the presence of context switches.

Pipeline stalls due to conditional branches represent one of the most significant impediments to realizing the performance potential of deeply pipelined, superscalar processors. Many branch predictors have been proposed to help alleviate this problem, including the Two-Level Adaptive Branch Predictor, and more recently, two-component hybrid branch predictors.In a less idealized environment, such as a time-shared system, code of interest involves context switches. Context switches, even at fairly large intervals, can seriously degrade the performance of many of the most accurate branch prediction schemes. In this paper, we introduce a new hybrid branch predictor and show that it is more accurate (for a given cost) than any previously published scheme, especially if the branch histories are periodically flushed due to the presence of context switches.

The Precomputed-Branch architecture: Efficient branches with compiler support

This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many intervals. This time-division parallelization is similar to the concept of trace-splitting parallelization but is completely different from this conventional technique because our simulator assures that its result is perfectly equivalent to what a sequential simulator produces. The assurance of the perfect accuracy is endued by a simple failure recovery mechanism; if i-th interval is simulated by a node with an approximate initial machine state which causes invalid result, the interval is simulated again by the node responsible to (i - 1)-th interval and thus having the correct state at the beginning of i-th interval. In order to reduce the possibility of the interval failure for efficiency, the fully cycle-accurate simulation for an interval is preceded by a partial and thus fast micro architectural simulation including that for caches, branch predictors and their interaction in speculative execution. Another important technique is to check the validity of an interval simulation by comparing approximate and correct initial states with respect to their effect to the subsequent execution, rather than the raw values of them. The effectiveness of these techniques are exhibited by our SimpleScalar-based implementation and its evaluation with SPEC CPU95 benchmarks which results that 8-node and 16-node parallel simulations achieve up to 5.8-fold and 9.4-fold speedup respectively

This paper proposes an architectural feature for superscalar processors called conditional annulling. The conditional annulling mechanism achieves both the effects of conditional execution and speculative execution without incurring a significant increase of hardware complexity and cost. All effectiveness evaluation carried out in this paper shows the conditional annulling mechanism is effective in improving superscalar processor instruction scheduling. >

Speculative execution is an important source of parallelism for VLIW and superscalar processors. A serious challenge with compiler-controlled speculative execution is to efficiently handle exceptions for speculative instructions. In this article, a set of architectural features and compile-time scheduling support collectively referred to assentinel schedulingis introduced. Sentinel scheduling provides an effective framework for both compiler-controlled speculative execution and exception handling. All program exceptions are accurately detected and reported in a timely manner with sentinel scheduling. Recovery from exceptions is also ensured with the model. Experimental results show the effectiveness of sentinel scheduling for exploiting instruction-level parallelism and overhead associated with exception handling.

This is a study of the formal verification of a VLIW microprocessor that imitates the Intel Itanium [9][12][17] in features such as predicated execution, register remapping, advanced and speculative loads, and branch prediction. The formal verification is done with the Burch and Dill flushing technique [5] by exploiting the properties of Positive Equality [3][4]. The contributions include an extensive use of conservative approximations in abstracting portions of the processor and a framework for decomposition of the Boolean evaluation of the correctness formula. The conservative approximations are applied automatically when abstracting a memory whose forwarding logic is not affected by stalling conditions that preserve the correctness of the memory semantics for the same memory. These techniques allow a reduction of more than a factor of 4 in the CPU time for the formal verification of the most complex processor model examined relative to the monolithic evaluation of the correctness formula for a version of the same processor where conservative approximations are not applied.

Due to the prohibitive cost of worst-case timing analysis for modern processors, the design of time-predictable processors has become increasingly important for hard real-time and safety-critical systems. However, to the best of our knowledge currently there is no effective and widely accepted metric to quantitatively evaluate time predictability of processors, which greatly impedes the advancement of time-predictable processor design. This paper first introduces the concept of architectural time predictability (ATP), which separates timing uncertainty concerns caused by hardware from software. We then propose a metric called Architectural Time-predictability Factor (ATF) to measure architectural time predictability. Our evaluation on a Very Long Instruction Word (VLIW) processor indicates that ATF is an effective metric to quantitatively evaluate architectural time predictability of a whole processor as well as its architectural and microarchitectural components such as caches, branch prediction, speculative execution, parallel pipelines, and Scratch-Pad Memory (SPM). Thus ATF can be used to quantitatively guide architectural design for enhancing time predictability or making better trade-offs between performance and time predictability.

It has been shown that control flow decisions often reduce the amount of fine-grain, or instruction-level parallelism in many computations. There exists various architectural solutions to this problem, such as branch prediction and speculative execution. Here we present an alternative solution, based on the use of partial evaluation for statically increasing the parallelism of a computation. In particular we explore the capability of a partial evaluator to remove control flow decisions.A partial evaluator is described, which specializes data flow graphs produced by a compiler for a fine-grained processor array. The data flow graphs can be viewed as the equivalent of a machine-code program for conventional processor, and consequently some aspects of the architecture can be taken into account by the partial evaluator.Results from the use of the partial evaluator show that it can significantly improve the performance of a computation. The performance improvement is partly due to improved parallelism, but mostly due to a reduce dynamic instruction count, i.e. a reduction in the number of operations executed.

Branch misprediction is one of the important causes of performance degradation in superpipelined and superscalar processors. Most of the existing branch predictors, based on the exploiting of branch history, suffer from prediction accuracy decrease caused by frequent context switches. The goal of this research is to reduce misprediction rate (MPR) when the context switches are frequent, and not to increase the MPR when the context switches are relatively rare. We propose two independent, but closely related modifications of global adaptive prediction mechanisms: first, to flush only the branch history register (BHR) at context switch, instead of reinitialization of the whole predictor, and second, to use two separated BHRs, one for user and one for kernel branches, instead of one global history register. We have evaluated the ideas by measurements on real traces from IBS (Instruction Benchmark Set), and have shown that both modifications reduce MPR at negligible hardware cost.

High-performance superscalar processors, which can be used in building base-stations of cell phones and cloud-based web servers, rely heavily on aggressive branch predictors to avoid stalls no matter the branch is taken or not. Dynamic branch predictor which is based on the historical records of the previously executed branches always outputs good performance. Two-bit predictor discussed in this paper is one of the most popular ones that always practically employed. This paper demonstrates two implementations of two-bit predictors. Using BTB to process solo conditional branches is the first one, which is normally used. Other categories of branch instructions may results in several bubbles as the penalty. While the other implementation employs BTB dealing with all kinds of branch instructions, generating target addresses without any delay cycle. Simulation results show that the second implementation has much better performance than the former one. It decreases the mis-prediction rate from 12.26% to 11.48%, and also has much higher prediction accuracy on indirect jumps. With these results, we have our predictor re-designed accordingly and implemented successfully in superscalar processors.

A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. This paper presents a novel cost-effective mechanism called the two-block ahead branch predictor. Information from the current instruction block is not used for predicting the address of the next instruction block, but rather for predicting the block following the next instruction block.This approach overcomes the instruction fetch bottle-neck exhibited by wide-dispatch brainiac processors by enabling them to efficiently predict addresses of two instruction blocks in a single cycle. Furthermore, pipelining the branch prediction process can also be done by means of our predictor for speed demon processors to achieve higher clock rate or to improve the prediction accuracy by means of bigger prediction structures.Moreover, and unlike the previously-proposed multiple predictor schemes, multiple-block ahead branch predictors can use any of the branch prediction schemes to perform the very accurate predictions required to achieve high-performance on superscalar processors.