Enriching C-based High-Level Synthesis with parallel pattern templates

High-Level Synthesis (HLS) tools are aimed at enabling performant FPGA designs that are authored in a high-level language. While commercial HLS tools are available today, there is still a substantial performance gap between most designs developed via HLS relative to traditional, labor intensive approaches. We report on several cases where an anticipated performance improvement was either not realized or resulted in decreased performance. These include: programming paradigm choices between data parallel vs. pipelined designs; dataflow implementations; configuration parameter choices; and handling odd data set sizes. The results point to a number of improvements that are needed for HLS tool flows, including a strong need for performance modeling that can reliably guide the compilation optimization process.

The potential of FPGAs as accelerators for high-performance computing applications is very large, but many factors are involved in their performance. The design for FPGAs and the selection of the proper optimizations when mapping computations to FPGAs lead to prohibitively long developing time. Alternatives are the high-level synthesis (HLS) tools, which promise a fast design space exploration due to design at high-level or analytical performance models which provide realistic performance expectations, potential impediments to performance, and optimization guidelines. In this paper we propose the combination of both, in order to construct a performance model for FPGAs which is able to visually condense all the helpful information for the designer. Our proposed model extends the roofline model, by considering the resource consumption and the parameters used in the HLS tools, to maximize the performance and the resource utilization within the area of the FPGA. The proposed model is applied to optimize the design exploration of a class of window-based image processing applications using two different HLS tools. The results show the accuracy of the model as well as its flexibility to be combined with any HLS tool.

To offset the high engineering cost of digital circuit design, hardware engineers are looking increasingly toward high-level languages such as C and C++ to implement their designs. To do this, they employ High-Level Synthesis (HLS) tools that translate their high-level specifications down to a hardware description language such as Verilog. Unfortunately, HLS tools themselves employ sophisticated optimization passes that may have bugs that silently introduce errors in realized hardware. The cost of such errors is high, as hardware is costly or impossible to repair if software patching is not an option. In this work, we present a translation validation approach for verifying the correctness of the HLS translation process. Given an initial C program and the generated Verilog code, our approach establishes their equivalence without relying on any intermediate results or representations produced by the HLS tool. We implemented our approach in a tool called VTV that is able to validate a body of programs compiled by the Xilinx Vivado HLS compiler.

Interface Synthesis in High-Level Synthesis (HLS) tool is the process by which it creates hardware interfaces from the formal C++ arguments of the C++ function being synthesized. The synthesis step uses size information from the C++ types along with user constraints and the interface components available in the libraries in order to identify the resources that can meet the user's constraints. During scheduling, the appropriate quantity of interface resources will be allocated and inserted into the resulting RTL netlist generated by the HLS tool. Interface Synthesis components can be simple wires, basic protocol req/ack like, or more sophisticated bus-protocol (masters and/or slaves). This work describes the design and the integration of a custom 10 component implementing STMicroelectronics proprietary STBus Type 3 protocol. STBus is a set of protocols, interfaces, primitives and architectures specifying an interconnect subsystem, versatile in terms of performance, architecture and implementation. The STBus includes heavy-pipelined transactions and out- of-order management.

Hardware Trojans are a major concern for integrated circuits. All parts of the electronics supply chain are vulnerable to this threat. Trojans can be inserted directly by a rogue employee or through a compromised computer-aided design tool at each step of the design cycle, including an alteration of the design files in the early stages and the fabrication process in a third-party malicious foundry. While Trojan insertion during the latter stages has been largely investigated, we focus on high-level synthesis (HLS) tools as a likely attack vector. HLS tools are used to generate intellectual property blocks from high-level specifications. To demonstrate the threat, we compromised an open-source HLS tool to inject three examples of HLS-aided hardware Trojans with functional and nonfunctional effects. Our results show that a black-hat HLS tool can be successfully used to maliciously alter electronic circuits to add latency, drain energy, or undermine the security of cryptographic hardware cores. This threat is an important security concern to address.

A common use for Field-Programmable Gate Arrays (FPGAs) is the implementation of hardware accelerators. A way of doing so is to specify the internal logic of such accelerators by using Hardware Description Languages (HDLs). However, HDLs rely on the expertise of developers and their knowledge about hardware development with FPGAs. Regarding this, efforts have been focused on developing High-level Synthesis (HLS) tools in an attempt to increase the overall abstraction level required for using FPGAs. However, the solutions presented by such tools are commonly considered inefficient in comparison to the ones achieved by a specialized hardware designer. An alternative solution to program FPGAs is the use of Domain- Specific Languages (DSLs), as they can provide higher abstraction levels than HDLs still allowing the developers to deal with specific issues leading to more efficient designs and not always covered by HLS tools. In this paper we present our recent work on a DSL named LALP (Language for Aggressive Loop Pipelining), which has been developed focusing on the development of FPGAbased, aggressively pipelined, hardware accelerators. We present the recent LALP extensions and the challenges we are facing regarding to the compilation of LALP to FPGAs.

Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy register-transfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment. To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code. Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code. The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

Domain-specific systems improve the performance of specific applications compared to general-purpose processing systems by deploying custom hardware accelerators. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools enable a comprehensive design space exploration, optimizing the accelerators' compute performance. However, they often ignore the challenges of implementing the accelerators in a system-on-chip, particularly how they access memory. Our work introduces a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the buffering system parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8× performance improvements while lowering memory channel utilization by 53.2% for a set of PolyBench kernels.

The GHKSS nonlinear projective filtering method as a representative of nonlinear time series analysis, has been used as a “posterior filtering” noise reduction technique in a range of applications. Compared to Fourier and model-based techniques it has the advantage of reducing the noise with broadband spectra, without knowledge of the system model. The contamination of time series data with measurement noise may result in an apparent loss of intrinsic dynamical information of the nonlinear systems. A real-time implementation and working principle of the GHKSS algorithm is widely ignored due to its complexity and high computational cost. Here, we present a real-time implementation of this algorithm using a Field Programmable Gate Array (FPGA) and High-level synthesis (HLS) tools. The computational burden is reduced by running the false nearest neighbour (FNN) search and delay estimation part of the GHKSS, on a separate DSP slice using HLS tools. The effect of noise reduction on dynamic preservation using GHKSS was illustrated by estimating the correlation dimension and the maximal Lyapunov exponent of the 3-D Chay model in the chaotic regime. This research is important since the real-time implementation of the GHKSS algorithm will widen its application in nonlinear time series analysis.

During the 1990s, High Level Synthesis (HLS) slowly started emerging to allow designers to cope with the ever-increasing complexity of digital signal processing systems such as wireless receivers. Only recently, a new generation of high-quality commercial HLS tools capable of generating decent RTL architectures from algorithmic-style code has become available. Although these tools are now starting to be adopted for actual designs, detailed experiences and results for these tools in significant designs is still lacking. In this work we have analyzed the design process of a significant portion of a wireless communication application using AutoESL's AutoPilot HLS tool. We target a Xilinx Virtex-5 FPGA device and a clock frequency of 225 MHz. We have compared our HLS implementation to a reference implementation obtained using manual RTL design methods. We found that our HLS implementation is competitive to this reference implementation in terms of throughput and resource cost. The time needed to obtain a first HLS implementation matching throughput and resource cost aspects of the reference implementation is similar to the design time of the reference implementation. After obtaining a first HLS implementation, we were able to explore and implement different application architectures with HLS in only a couple of hours, thereby gaining significant savings in design time over manual RTL design, where architectural exploration may take weeks.

The article is devoted to a research of an efficiency of high-level synthesis approach, based on Xilinx’s high-level synthesis tool - Vivado, for a hardware implementation of sorting algorithms, which are one of the key algorithms for Big Data analysis, Data Mining, Data and Management. Performance and hardware costs are the measures of the efficiency in the provided research. The research methods are simulation and comparative analysis. Efficiency of software implementation of the selected sorting algorithms, based on a universal processor, is compared with efficiency of hardware implementation of the same sorting algorithms, obtained by high-level synthesis procedure with help of Xilinx’s high-level synthesis tool. The article discusses approaches to optimize the description of the sorting algorithms and assignments in boundaries of high-level synthesis procedure to achieve optimal efficiency of the final hardware solutions. The article shows that the main efficiency gain is determinate by the internal features of the sorting algorithm, selected for hardware implementation; the ability to parallelize the processing of the source arrays, which is achieved both by the settings of the Vivado synthesis tool and description style used for source code. Article highlights research results and provide a direction for the future research works.

High-level synthesis (HLS) tools streamline FPGA design by enabling engineers to implement hardware using $\mathrm{C} / \mathrm{C}++$ languages. However, while clock management serves as a critical stage in the FPGA EDA flow that affects system-level performance, area, and especially power consumption, existing commercial HLS tools lack comprehensive solutions for clock management. Specifically, the diversity of clock resources creates a vast design space for finding the optimal configuration, and the insufficient analysis of multiple clock domain scenarios hinders effective clock-oriented optimizations in HLS. This work introduces AutoClock, an open-source integrated clock management framework that complements AMD Vitis HLS. AutoClock allocates resources for clock generation, assigns modules to appropriate clock domains, addresses metastability and time division multiplexing (TDM) malfunctioning introduced by multiclock domain architectures, and hierarchically gates the clock of modules in a design. Experimental results demonstrate that AutoClock can fully utilize clock resources on FPGAs and help reduce dynamic power consumption by up to 74.38%.

Classical strategies in design for testability are applied at the gate-level, after the RT-logic synthesis process. New techniques covering test and synthesis (Test Synthesis) are appearing but their application is mainly oriented to gate level (commercial tools such as Synopsys). On the other hand, most high-level synthesis tools do not take into account the testability of the final architecture. This paper presents a high-level synthesis system which includes testability improvement among its goals. The aforementioned system generates loop free circuits and are, therefore, easily testable with partial scan techniques. In order to achieve this, a complete RT-level loop classification is made and the origin at the algorithmic level is analyzed in order to avoid loops during the synthesis process, not only in the data path but also in the controller. With the usual high-level synthesis benchmarks, the proposed system reaches 100% fault coverages with a smaller area than other high-level synthesis tools.

Multiplication is a common operation in many applications and there exist various types of multiplication operations. Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources. This paper proposes algorithms for automatically identifying the different types of multiplication operations and investigates the ensemble of these different types of multiplication operations. This distinguishes it from previous works where mapping strategies for an individual type of multiplication operation have been investigated and the type of multiplication operation is assumed to be knowna priori. A new cost model, independent of device and synthesis tools, for establishing priority among different types of multiplication operations for mapping to on-chip DSP blocks is also proposed. This cost model is used by a proposed analysis and priority ordering based mapping strategy targeted at making efficient use of hard DSP blocks on FPGAs while maximizing the operating frequency of designs. Results show that the proposed methodology could result in designs which were at least 2× faster in performance than those generated by commercial HLS tool: Vivado-HLS.

High-Level Synthesis (HLS) has multiple significant advantages over traditional RT-level design flows. One in particular that we address in this work is the ability to generate multiple functional equivalent design variants with unique trade-offs like area, performance and power from the same behavioral description. This is typically done by setting synthesis options in the form or pragmas (comments) to mainly control how to synthesize arrays (RAM or registers), loops (unroll, partially unroll, no unroll or pipeline) and functions (inline or not). Setting different pragma combinations lead to these different design implementations. Out of all the pragma combinations the designer is typically only interested in those that lead to the Pareto-optimal designs. Fortunately, this search can be automated, but unfortunately, the search space to find these pragma combinations grows supra-linearly with the number of pragma settings. Thus, fast and efficient heuristics are needed. These heuristics generate a new pragma combination and then evaluate their effect by synthesizing (HLS) it. The most time-consuming part of this process is having to execute a full synthesis (HLS) on the behavioral description for every new pragma combination. One obvious way to accelerate the exploration is to parallelize the exploration process using a multithreaded heuristic. The theoretical speedup should match the number of parallel threads. The main problem with this approach is that every HLS invokation requires to check out a HLS tool license. This license is not released until the synthesis process has finished. This implies that the maximum number of parallel threads is restricted by the number of available licenses, which in the ASIC case are extremely expensive. On the contrary, FPGA vendors make their HLS tools free. Thus, it is tempting to investigate if FPGA HLS tools can be used to find the Pareto-optimal designs in the ASIC case. To address this, in this work we present a dedicated multithreaded parallel HLS design space explorer (DSE) based on transfer learning that is able to accelerate HLS DSE for ASICs by targeting first FPGAs and using machine learning to convert the exploration results obtained to find the optimal ASIC equivalent. Experimental results show the effectiveness and robustness of our approach.