Ensemble learning based Architecture Vulnerability Factor calculation using partial feature set in processors

The technique known as ACE Analysis allows researchers to quantify a hardware structure's Architectural Vulnerability Factor (AVF) using simulation. This allows researchers to understand a hardware structure's vulnerability to soft errors and consider design tradeoffs when running specific workloads. AVF is only applicable to hardware, however, and no corresponding concept has yet been introduced for software. Quantifying vulnerability to hardware faults at a software, or program, level would allow researchers to gain a better understanding of the reliability of a program as run on a particular architecture (e.g., X86, PowerPC), independent of the micro-architecture on which it is executed. This ability can provide a basis for future research into reliability techniques at a software level.In this work, we adapt the techniques of ACE Analysis to develop a new software-level vulnerability metric called the Program Vulnerability Factor (PVF). This metric allows insight into the vulnerability of a software resource to hardware faults in a micro-architecture independent way, and can be used to make judgments about the relative reliability of different programs. We describe in detail how to calculate the PVF of a software resource, and show that the PVF of the architectural register file closely correlates with the AVF of the underlying physical register file and can serve as a good predictor of relative AVF when comparing the AVF of two different programs.

We propose AVGI, a new Statistical Fault Injection (SFI)-based methodology, which delivers orders of magnitude faster assessment of the Architectural Vulnerability Factor (AVF) of a microprocessor chip, while retaining the high accuracy of SFI. The proposed methodology is based on three key insights about the way that faults traverse complex out-of-order microarchitectures: (1) the distribution of the different ways that hardware faults manifest at the software (i.e., the first effects of faults to the software layer) is relatively uniform across workloads, (2) the final effects of faults in a specific hardware structure (i.e., their effect on the program execution) is relatively uniform for different workloads and depends on the distribution of the above fault manifestations, and (3) the majority of first manifestations occur in certain timeframe from the fault occurrence, which is significantly shorter than the complete execution of the workload, and depends on the type of hardware structure. Based on these insights, the proposed AVGI methodology accurately estimates the complete cross-layer vulnerability (i.e., AVF) for every hardware structure in fine granularity (SDCs and Crashes). Our experimental analysis shows that preserving high levels of accuracy, the proposed AVF assessment methodology is up to 337x and 440x faster than an accelerated exhaustive SFI, for two different microarchitectures of 64-bit Armv8 and 32-bit Armv7 CPU models, respectively.

As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior research has shown that there is significant architecture-level masking, and many soft error solutions take advantage of this effect. Prior work has also shown thatthe degree of such masking can vary significantly across workloads and between individual workload phases, motivating dynamic adaptation of reliability solutions for optimal cost and benefit. For such adaptation, it is important to be able to accurately estimate the amount ofmasking or the architecture vulnerability factor (AVF) online, while the program is running. Unfortunately, existing solutions for estimating AVF are often based on offline simulators and hard to implement in real processors. This paper proposes a novel way of estimating AVF online, using simple modifications to the processor. The estimation method applies to both logic and storage structures on the processor. Compared to previous methodsfor estimating AVF, our method does not require any offline simulation or calibration for different workloads. We tested our method with a widely used simulator from industry, for four processor structures and for 100 to 200 intervals of each of eleven SPEC benchmarks. The results show that our method provides acceptably accurate AVF estimates at runtime. The absoluteerror rarely exceeds 0.08 across all application intervals for all structures, and the mean absolute error for a given application and structure combination is always within 0.05.

The adoption of cloud computing has grown significantly among individuals and in organizations. According to this growth, Cloud Service Providers have continuously expanded and updated cloud-computing infrastructures, which have become more heterogeneous. Managing these heterogeneous resources in cloud infrastructures while ensuring Quality of Service (QoS) and minimizing energy consumption is a prominent challenge. Therefore, unifying energy consumption models to deal with heterogeneous cloud environments is essential in order to efficiently manage these resources. This paper deeply analyzes factors affecting power consumption and employs these factors to develop power models. Because of the strong correlation between power consumption and energy consumption, the influencing factors on power consumption, with the addition of other factors, are considered when developing energy consumption models to enhance the treatment in heterogeneous infrastructures in cloud computing. These models have been developed for two Virtual Machines (VMs) containing heterogeneous Graphics Processing Units (GPUs) architectures with different features and capabilities. Experiments evaluate the models through a cloud testbed between the actual and predicted values produced by the models. Deep Neural Network (DNN) power models are validated with shallow neural networks using performance counters as inputs. Then, the results are significantly enhanced by 8% when using hybrid inputs (performance counters, GPU and memory utilization). Moreover, a DNN energy-agnostic model to abstract the complexity of heterogeneous GPU architectures is presented for the two VMs. A comparison between the standard and agnostic energy models containing common inputs is conducted in each VM. Agnostic energy models with common inputs for both VMs show a slight enhancement in accuracy with input reduction.

Accelerated assessment of fine-grain AVF in NoC using a Multi-Cell Upsets considered fault injection

On the path to Exascale, the goal of High Performance Computing (HPC) to achieve maximum performance becomes the goal of achieving maximum performance under strict power constraint. Novel approaches to hardware and software co-design of modern HPC systems have to be developed to address such challenges. In this paper, we study prediction of power consumption of HPC systems using metrics obtained from hardware performance counters. We argue that this methodology is portable across different micro architecture implementations and compare results obtained on Intel 64, IBMR and Cavium ThunderXR ARMv8 microarchitectures.We discuss optimal number and type of hardware performance counters required to accurately predict power consumption.We compare accuracy of power predictions provided by models based on Linear Regression (LR) and Neural Networks (NN). We find that the NN-based model provides better accuracy of predictions than the LR model. We also find, that presently it is not yet possible to predict power consumption on a given microarchitecture using data obtained on a different microarchitecture. Results of our work can be used as a starting point for developing unified, cross-architectural models for predicting power consumption.

This paper examines the single-event upset response of a customer memory interface design on the Xilinx 20nm XCKU040 Field Programmable Gate Array (FPGA) irradiated with 64MeV proton source. Results for single-event upsets on configuration RAM (CRAM) cells are provided. The difference between architectural vulnerability factor (AVF) and design vulnerability factor (DVF) of the customer memory interface design is also discussed in this work.

Issue queue is a critical structure in the pipeline and more vulnerable to soft-error strikes. Reducing soft error vulnerability of issue queue cannot be ignored in microprocessor reliability design. Instructions clog in issue queue caused by instruction flow mix and functional unit configuration mismatch. That makes the soft error vulnerability of issue queue increases. This paper proposed a vulnerability mitigation method which does not need to change functional unit configuration. It adjusted the instruction flow mix in issue queue, reduced the waiting time of instruction in issue queue to reduce the architectural vulnerability factor. The experiment result shows that average reduces of architectural vulnerability factor are 2.8% and improvement of reliability-performance is 4.9%.

Since the Reliability is a significant need for most of the Multicore systems, using fault-tolerant techniques such as hardware replication and software re-execution have been prevalent. This paper presents an adaptive fault-tolerant task scheduling algorithm that is a combination of TMR and DMR algorithms, in which Architectural Vulnerability Factor is considered in scheduling decisions, besides EDF and LLF scheduling algorithms. The proposed algorithm has been evaluated and compared with TMR and DMR methods in total execution time and processing cores utilization considering 3 to 8 cores. According to the results our proposed fault-tolerant methods outperforms both TMR and DMR methods about 35% in average.

Summary form only given. In this talk, the author outlines how the soft error problem is affecting microprocessor design, how to compute the AVFs for various processor structures, and how to estimates AVFs at run-time using a new concept called quantized AVFs.

Advances in VLSI technology have made circuits more vulnerable to faults. Architectural vulnerability factor (AVF) reflects the possibility that a transient fault eventually causes an error in the circuit output. This factor represents the system vulnerability to transient faults and is used to compare different fault-tolerant designs or architectures. In this paper, we have introduced a simulation-based fault injection framework which is developed to evaluate the AVF of different adder hardware description models in various abstraction levels. Then, we introduce the most beneficial abstraction level for evaluating the vulnerability of a design. Finally, exploiting our fault injection framework, we compare the inherent fault tolerance of eight famous adders. We have explored the design space of different adder architectures while considering both delay and area constraints for comparing the inherent fault tolerance level of different adder architectures. To the best of our knowledge, this comparative study is not covered in the literature elsewhere.

Early reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural structures modeled in performance simulators is an accurate method to measure their Architectural Vulnerability Factor (AVF) but requires excessively long campaigns to obtain high statistical significance.

Protecting on-chip cache memories against soft errors has become an increasing challenge in designing new generation reliable microprocessors. Previous efforts have mainly focused on improving the reliability of the cache data arrays. Due to its crucial importance to the correctness of cache accesses, the tag array also demands high reliability against soft errors. Exploiting the address locality of memory accesses, we propose to duplicate most recently accessed tag entries in a small tag replication buffer (TRB) thus to protect the information integrity of the tag array in the data cache. Experimental results show that our proposed TRB scheme achieves a high 90% access-with-replica (AWR) rate with low performance (~0%), energy (16.3%), and area (19.9%) overheads. We also conduct a detailed design space exploration for the TRB design and propose a selective TRB scheme that achieves a higher AWR rate (97.4%) for the dirty cachelines with negligible overheads. To provide a comprehensive evaluation of the tag-array reliability, we further conduct an architectural vulnerability factor (AVF) analysis for the tag array in the data cache and propose a refined metric, detected-without-replica-AVF (DOR-AVF), which combines the AVF and AWR analysis. Based on our DOR-AVF analysis, a selective TRB scheme with early write-back (S-TRB-EWB) is proposed, which achieves a zero DOR-AVF and 100% AWR rate at a negligible performance overhead. Results from statistical fault/error injection experiment also confirm the effectiveness of our TRB schemes and the achieved reliability of the cache tag array that recovers 100% of detected errors.

Colleges and universities are large consumers of energy, with a huge potential for building energy efficiency, and need to reduce energy consumption to build a low-carbon, energy-saving campus. Predicting the energy consumption of campus buildings can help to accurately manage the electricity consumption of buildings and reduce the energy consumption of buildings. However, the electricity consumption of a building’s operation is affected by many factors, and it is difficult to establish a model for analysis and prediction. Therefore, in this study, the training building of the BIM education center on campus was selected as the research object, and a digital twin O&M platform was established by integrating IoT, digital twin technology (DDT), smart meter monitoring devices, and indoor environment monitoring devices. The O&M management platform can monitor real-time changes in indoor power consumption data and environmental parameters, and organize data on multiple influencing factors and power consumption. Following training, validation, and testing, the machine learning models (back propagation neural network, support vector model, and multiple linear regression model) were assessed and compared for accuracy. Following the multiple linear regression and support vector models, the backpropagation neural network model exhibited the highest accuracy. Consistent with the actual power consumption detection results in the BIM education center, the backpropagation neural network model produced results. Consequently, the BP model created in this study demonstrated its dependability and ability to forecast campus building power usage, assisting the university in organizing its energy supply and creating a campus that prioritizes conservation.

This paper demonstrates a first-order, linear power estimation model that uses performance counters to estimate run-time CPU and memory power consumption of the Intel PXA255 processor. Our model uses a set of power weights that map hardware performance counter values to processor and memory power consumption. Power weights are derived offline once per processor voltage and frequency configuration using parameter estimation techniques. They can be applied in a dynamic voltage/frequency scaling environment by setting six descriptive parameters. We have tested our model using a wide selection of benchmarks including SPEC2000, Java CDC and Java CLDC programming environments. The accuracy is quite good; average estimated power consumption is within 4% of the measured average CPU power consumption. We believe such power estimation schemes can serve as a foundation for intelligent, power-aware embedded systems that dynamically adapt to the device's power consumption.