Entering the hot zone

Welcome to the DATE 08 Conference Proceedings. DATE combines the world's favourite electronic systems design conference and Europe's leading international exhibition for electronic design, automation and test, from system level hardware and software implementation right down to integrated circuit design. The DATE 08 event features a technical program with 77 sessions covering the latest developments in system design and embedded software, IC design/test methodologies and EDA tools, together with an exhibition with the leading EDA, silicon and IP providers showing their new products and services. Challenges that you all face or soon will face in your daily practice are the increasing design complexity of highly integrated systems, the introduction of reconfigurability and embedded software, and the control of power and variability in nanometer IC designs. All these issues will be addressed in this year's DATE event. For the 11th successive year DATE has prepared an exciting technical programme, with the help of the more than 400 members of the Technical Programme Committee, who dedicated their time to thoroughly review the 839 submissions in 37 topics, ranging from system level down to circuit design and covering all the most relevant application domains. The submissions are organised in 4 major areas: D --- Design Methods, Tools, Algorithms and Languages A --- Application Design T --- Test Methods, Tools and Innovative Experiences E --- Embedded Software After a thorough review and selection process (with an average of 5 reviews per paper), finally 198 regular papers were selected for presentation at the conference. Additionally, there are 46 Interactive Presentations that are organised in 5 IP sessions. Together with the invited special sessions (panels, embedded tutorials and hot topic sessions), this has resulted in a high-quality technical program. The technical program provides a wide but high-quality coverage of design, design automation and test topics, from the system level to the integrated circuit level. Compared with previous years, submissions in the Embedded Software track has increased by 50%, showing a clear trend towards a comprehensive system design focus with integrated hardware and software solutions. DATE has established itself firmly as a true Electronic System Design Conference. This year the conference is held in Germany, at the ICM in Munich and spans an entire working week from Monday March 10 to Friday March 14. On Monday, eleven pre-conference tutorials will be given. The three-full day tutorials cover topics of great interest for system design. The first tutorial deals with techniques to automatically realising embedded system from high-level functional models. The second tutorial addresses the different issues related to communication based design and architectures in automotive electronic systems. The third tutorial discusses several key concepts on system-level design and application mapping for wireless and multimedia MPSoC architectures. Furthermore, eight half-day tutorials are also given, which cover a wide spectrum of topics on specification, modelling, design and test. The main conference opens on Tuesday March 11, with two very interesting and complementary keynote speeches. Dominique Vernay, Chief Technical Officer for Thales, will talk about the challenges of embedded systems design, and Giovanni de Micheli, Professor at EPFL, will present his views on designing micro/nano systems for a safer and healthier tomorrow. On the same day, the Executive Track offers a series of business panels with executives discussing hot topics in design: the perils of 45 nanometers, the changes in EDA strategies from IDM, to fablite to fabless, and embedded systems level design strategies. DATE 08 will again offer two specific days related to special themes. On Wednesday March 12, a special full-day track is devoted to Automotive Electronics---Software and Architecture. This special-day track will focus on the challenges faced by the automotive supply chain with particular attention to system and software architecture design. It provides a comprehensive analysis of the evolution of automotive architectures, including ECUs, sensors and communication standards and discusses how new methods, tools and standards for interoperability and component-based design can deal with the increasing complexity of software systems and their need for reliability and guaranteed timely behaviour. In addition, it addresses to what degree existing standards, including AUTOSAR and FLEXRAY and model-based development, can support the development of safety and time-critical software. On Thursday March 13, a second special full-day track focuses on Dependable Embedded Systems. This track will address both conceptual and applied issues for design, analysis and validation of dependable embedded systems. The utility of embedded systems and services is based, in large part, on our depending on their sustained functionality in spite of the encountered operational or malicious disruptions. As the number of transient and also permanent disruptions (given the decreasing device geometries, higher device density, lower voltage latching, faster clocks etc) is expected to increase substantially, this will not only be a key issue for the hardware community but also the systems community in general. Solutions using a combination of hardware and software might be more effective than hardware-only or software-only solutions. This track focuses on both conceptual and applied issues for design, analysis and validation of dependable embedded systems. Besides these special tracks, the main conference is organized in six parallel tracks of sessions, three devoted to design methods, tools, algorithms and languages, one to application design, one to test methods, tools and innovative experiences, and finally one to embedded software. The presentations of the selected regular papers in these parallel tracks are complemented by nine Special Sessions and two Invited Industrial Sessions. The special sessions are organized in the form of panels, hot topics, and embedded tutorials. The topics to be covered include quantitative evaluation for embedded systems design, design and manufacturing at 32 and 22nm, software for wireless networked embedded systems, test challenges for low power devices, quantitative productivity measurement in IC design, and 3D Integration. The two invited industrial sessions deal with industrial system designs in transportation and information technologies. To emphasise that DATE is the major event for the designers, DATE 08 features also invited sessions where Europe's famous consumer industry presents their best designs and design practices. Friday March 14 is the day for the DATE workshops. DATE 08 offers workshops on current and emerging important issues in design, test, EDA and software to complement the regular conference. They provide a unique opportunity for the various research and design communities to spend a day discussing the latest and the best, sharing their experiences and visions. This year's workshop program includes eight workshop themes. Four workshops are related to software engineering, ranging from dependable software to modelling, analysis and development tools. Four other workshop themes cover a variety of topics such as the impact of process variations on design and test, the merging world of Nano-Electro-Mechanical Systems, new directions in high level synthesis, and heterogeneous reconfigurable hardware. Each workshop features presentations, invited or submitted, from highly distinguished academic and industrial researchers. Finally, throughout the conference days, DATE offers a comprehensive overview of commercial design and verification tools in its large exhibition hall. Exhibitors include EDA vendors, silicon, FPGA and IP providers showing their new products and services. In addition, there is an Exhibition Theatre featuring talks from engineering managers of the leading electronic manufacturers on first-hand design experiences of commercial EDA tools. New this year is the European projects village where different European and large government funded projects will be able to show their ongoing research and results to the design community and have the opportunity for internal meetings and discussions. The DATE week will be also an opportunity for students and universities to show their research work, through the PhD Forum on Monday evening and the University Booth where hardware and software demonstrations will be shown by different universities on a rotation schedule. The DATE 08 event's program will be particularly attractive to industrial designers, at analog, IC, FPGA and embedded system level, as well as software designers, to researchers and academics as well as to design managers, and an increasing attendance is expected. We therefore invite you to take full advantage of the many opportunities offered to you by DATE 08, to extend your knowledge and/or business in electronic system's design and to exploit the abundant networking possibilities offered to socialise with colleagues, including fringe meetings and a memorable social party with bands and dancing. We hope that you will all enjoy the DATE 08 Conference and Exhibition.

We present a signal and thermal integrity (SI/TI) cooptimization framework for multi-chiplet placement and routing using generative adversarial imitation learning (GAIL). Design of modern 2.5-D integrated circuits face the critical challenge simultaneously optimizing TI and SI. GAIL goes beyond simply mimicking expert strategies by learning policies that generate consistent optimal behaviors across diverse state distributions, making it particularly well-suited for chiplet placement problems requiring simultaneous consideration of conflicting TI and SI objectives. Our approach leverages GAIL to learn placement strategies that effectively balance these competing objectives, incorporating both eye diagram-based signal quality metrics with turn penalties and power-aware thermal modeling. Experimental results demonstrate that our framework successfully achieves balanced optimization between thermal and SI constraints, enabling adaptive placement decisions for heterogeneous chiplet systems without requiring objective-specific retraining.

This paper investigates new solutions for improving the performance of high density Resistive Random-Access Memories (RRAM), based on novel architecture and on the use of alternative materials. Starting from the conventional architecture, which integrates in a crossbar structure many elementary cells composed by one diode and one RRAM (1D1R), here an alternative reverse (1D1R-1R1D) architecture is proposed. This solution doubles the number of cells in a fixed volume and makes more efficient the bias management. An accurate electrothermal modeling is here carried out to check the obtained performance in terms of signal and thermal integrity. The use of the proposed architecture, along with a suitable choice of materials, including novel carbon nanomaterials, can solve or at least mitigate the electrical and thermal crosstalk problems, which are known to be critical for the RRAM crossbar configurations. A case-study is carried out, where a 3×3×4 crossbar structure is analyzed by means of a full 3D electrothermal model.

Technical system design processes are typically based on systems engineering vee models where designers move between functional and physical domains as they develop detailed designs of the overall system and its sub-systems and component parts. The movements between the functional and physical domains are informed by the core activities of any design process: synthesis, description, analysis and simulation, and decision-making. However, delivering socio-technical systems design mindsets, such as those needed to design multi-team systems, requires a new branch of systems science that integrates human behavior into system behavior. Design processes built on such a science would allow system designers to compare alternative solutions in terms of their anticipated performance and consider different options with respect to functions carried out by humans and machines. In this chapter we use a systems design process vee model and apply it to a case study that involves the design of a multi-team customer service system. Both the application of the vee model (i.e., the proposed design process) and the results of its application (i.e., the multi-team customer service system) can be regarded as socio-technical systems and are used to illustrate and elaborate on Clegg’s (Appl Ergon 31(5):463–477, 2000) socio-technical principles for system design. On this basis, we provide a practical framework for designing socio-technical systems and identify requirements for developing future methods and tools to support this process.

Discrete event simulation as an ergonomic tool to predict workload exposures during systems design

Power integrity (PI) has been an important technological issue in the field of electronic circuits and systems. It has been addressed in important papers using several different approaches [1][2]. The latest concept of the best PI condition is a low impedance between the power and ground lines or planes, that can be maintained regardless of the clock frequency, even in the GHz region. A novel technology was used in our previous study, in which a metal particle conductive layer (MPCL) was used instead of a copper plane [3][4]. This structure improved the PI for any clock frequency, particularly in the GHz region. The MPCLs consist of micrometer sized silver flakes (SF) and binder resin. In this study, we used an epoxy as a binder for conductive paste and polyimide (PI) copper clad laminate (CCL) as the inner dielectric of test coupons. These are general-use material so that they can be made easily, and apply to printed circuit boards (PCBs) and package substrates (PKGs). It has been found from transmission line test coupon measurements, that energy propagation time and frequency characteristics, are strongly affected by the metal particle content and chemical composition. From power/GND plane test coupon measurements, MPCL can reduce Z11 about 70% compared with copper plane from 1 to 5GHz frequency region. In this paper, we reveal the detail phenomena of MPCL exceed the region of usual transmission line theory and some critical factors to improve PI using MPCL.

A typical IC designer is familiar with the procedures, terminology and circuit analysis tools that are typical to a SPICE-like simulator environment. On the other hand, the microwave telecom system designers are using different methodology and tools (i.e. Smith chart), that help them proceed with their designs in an effective and proper way. The RF IC designer (especially if he comes from the low-frequency integrated circuit design field), must be familiar with the basic terminology and definitions employed in high-frequency telecom system design in order to be able to proceed with his work. For this purpose, in the present chapter, the basic definitions and terminology employed in telecommunications systems design will be briefly reviewed. Please note that the definition of phase noise will be postponed until Chapter 7 where the oscillator circuits are presented.

This paper presents some of the issues of signal and power integrity in relation with appropriate modeling and simulation methods that are available. The clock signal of a communication protocol is experimentally tested in order to find the rules to improve its signal integrity (SI) along the paths on the printed circuit board (PCB). The signal and power integrity of this PCB are improved using a set of experimental rules based on results of an experimental case study over signal routes. The experimental results obtained are compared with those given by the auto routing function of the design environment. Thus, some improvements of signal integrity along the route clock are highlighted. This set of rules applied to PCB design is validated by the experiment and simulation results.

The rapid advancement of artificial intelligence (AI) has accelerated the semiconductor industry, driving chip performance requirements to unprecedented levels. However, conventional system-on-chip (SoC) designs are increasingly constrained by the physical and economic limits of monolithic scaling, where continued transistor miniaturization yields diminishing returns and rising fabrication costs. To address these challenges, the industry has shifted toward chiplet-based heterogeneous integration and advanced packaging technologies. By interconnecting multiple specialized chiplets through high-density, high-bandwidth interfaces, this modular approach improves scalability, reusability, and cost efficiency while enabling faster time-to-market. However, chiplet-based systems introduce significant design complexity, particularly in signal integrity (SI) and power integrity (PI), where highly constrained interconnects and power delivery networks must meet stringent electrical requirements. Traditional design methodologies rely heavily on expert-driven manual tuning and extensive full-wave electromagnetic simulations using electronic design automation (EDA) tools, resulting in long design cycles that can span weeks or months. To overcome these limitations, this thesis investigates the application of AI, particularly deep reinforcement learning (RL), to automate and optimize chiplet-based system design with a focus on SI and PI challenges in advanced packaging technologies. The research initially explores a supervised learning approach using convolutional neural networks (CNNs) to classify signal impairments from eye diagrams. While effective, this approach reveals a critical dependence on large labeled datasets, which are scarce in SI/PI domains, motivating a shift toward RL for autonomous design space exploration without labeled data. The first major contribution proposes an RL framework for automated power distribution network (PDN) design in a four-chiplet system. Two RL algorithms, Dueling Double Deep Q-Network (DDDQN) and Proximal Policy Optimization (PPO), are evaluated under different reward strategies. Results show that dense analytical rewards based on power domain squareness and bump proximity enable the RL agent to achieve lower self-impedance than human-designed PDNs, ensuring power integrity across 28 power domains. The complete PDN layout, which typically requires three months of manual effort, is generated in under one hour using a single GPU. The second contribution focuses on signal integrity optimization for chiplet interconnects in CoWoS redistribution layers (RDLs). An RL agent is trained using a reward function that balances eye width, voltage transfer function (VTF) crosstalk, and interconnect density. The agent explores design variations across data rates from 4 to 32 GT/s using a simulation environment integrated with commercial EDA tools. Experimental results demonstrate up to 24.67% improvement in eye width and over 22 dB reduction in VTF crosstalk while satisfying UCIe electrical specifications. The training process also generates labeled datasets for future supervised learning. The third contribution introduces an RL-based routing framework for UCIe bridge interconnects in advanced System-in-Package (SiP). Using Proximal Policy Optimization, the framework learns to generate routing layouts that comply with constraints such as ground-signal-ground structures, layer assignment, and congestion avoidance. It supports all UCIe module configurations and produces design rule check-compliant solutions within 100 training episodes, reducing design time from four weeks to less than one hour while improving signal distribution and reducing via usage. In summary, this thesis presents a unified AI-driven methodology for addressing SI and PI challenges in chiplet-based systems. The proposed RL frameworks significantly outperform traditional design approaches in both efficiency and quality, demonstrating the potential of deep RL to enable scalable and intelligent design automation for advanced packaging and chiplet-based architectures.

Wen-Sheng Zhao from Hangzhou University, China, talks to Electronics Letters about the paper ‘Novel electromagnetic bandgap structure for wideband suppression of simultaneous switching noise’, page 1243 Wen-Sheng Zhao My research fields include interconnect modelling, multiphysics simulations and microwave sensor design. My major research topic is signal and power analysis of silicon via (TSV)-based 3D integrated systems. In recent years, the fourth industry revolution has shown an urgent need to develop next generation memory modules. As a key technology of industry 4.0, TSV-based high-bandwidth memory (HBM) has attracted a lot of interest from both the research and industrial worlds. To guarantee the system performance, it is necessary to perform signal/power/thermal integrity analysis for an HBM module. We are currently working on the issues related to the physical design of HBM modules (such as TSV modeling, equaliser design, and power noise suppression). Modern circuits are developing towards miniaturisation, high frequency and low power consumption, which puts strict constraints on the signal and power integrity design. For example, the operating voltages are continuously lowered, thereby limiting noise margin in power distribution network (PDN). Under such circumstances, power/ground noise is becoming a serious problem. To resolve this issue, various techniques including decoupling capacitor and electromagnetic bandgap (EBG) have been proposed and are under study. In comparison with decoupling capacitor, EBG structure can provide wideband noise suppression, and has been widely explored in the chip, package, and board. To improve the system performance, it is always desirable to increase the stopband bandwidth and rejection level of EBG structure. In this Letter, a power plane with coplanar EBG etched in the S-bridge EBG was proposed. With the proposed EBG structure, an ultrawide bandgap from 0.28 to 25 GHz with a high suppression level of -45 dB was achieved. Moreover, the signal integrity performance of the proposed EBG power plane was examined. The signal integrity can be ensured by utilising differential traces as the transmission structure. The proposed design can be used to reduce power/ground noise efficiently for mixed signal systems. We expect the proposed design to provide performance improvements in various mixed-signal systems in the immediate future. Currently, we are also working on developing EBG structures for silicon interposer and on-chip PDN. In the longer term, we expect that the EBG structures can be further explored and used in the physical design optimisation of HBM systems. As the clock frequency of the circuit system is continuously increased, the frequency of the simultaneous switching noise (SSN) also increases. However, the low-frequency components of the noise are not reduced accordingly. Therefore, the major issue we faced was developing a wide stopband EBG structure with a low cutoff frequency. Moreover, as grooves etched on the power/ground plane have an adverse impact on the signal transmission, we had to pay special attention to ensure signal integrity in the EBG design procedure. When we began studying TSV technologies, there was very little real-world deployment. Although several semiconductor giants such as Samsung presented some TSV based memory modules, these systems remained in the laboratory stage. Nowadays, TSV technology has matured, and the TSV-based HBM modules have been used in many graphics processing units since 2015. We are currently working on the physical design and optimisation (including signal and power integrity analysis) for TSV-based integrated systems. We have seen the introduction of many kinds of techniques (e.g., EBG, equaliser, differential signaling, and active decoupling) which will be helpful for future designs. There is no doubt that further improvements are always desirable to promote wide applications of TSV based integrated systems.

From the Publisher: Models in System Design tracks the general trend in electronics in terms of size, complexity and difficulty of maintenance. System design is by nature combined with prototyping, mixed domain design, and verification, and it is no surprise that today's modeling & models are used in various levels of system design and verification. In order to deal with constraints induced by volume and complexity, new methods and techniques have been defined. Models in System Design provides an overview of the latest modeling techniques for use by system designers. Models in System Design will help designers and researchers to understand these latest techniques in system design and as such will be of interest to all involved in embedded system design.

In this paper, we firstly proposed and electrical and thermal co-analyzed a novel through mold plate (TMP) for thermal management of high bandwidth memory (HBM). Thermal issues are bottlenecks in the development of HBM and 2.5-D/3-D ICs. The proposed TMP can be one of the promising solutions for advanced thermal management. Thermal coupling from the graphic processing unit (GPU) is the dominant factor for HBM thermal issues. A new thermal path can be achieved by installing the TMP in the epoxy molding compound (EMC) between GPU and HBM to significantly prevent thermal coupling from the GPU. By using 3D electromagnetic and fluent simulation, we verified the proposed TMP based on co-analysis of signal integrity (SI) and thermal integrity (TI). SI analysis considering both TMP and operating temperature provided the thermal and electrical superiority of TMP. As a result, the results showed the improvement of thermal integrity and signal integrity of the HBM by not only reducing HBM junction temperature by 10.3 °C but also decreasing jitter by 4.54 % compared to a conventional HBM graphic module.

The environmental impact of servers and datacenters is an important future challenge. System architects have traditionally focused on operational energy as a proxy for designing green servers, but this ignores important environmental implications from server production (materials, manufacturing, etc.). In contrast, this paper argues for a lifecycle focus on the environmental impact of future server designs, to include both operation and production. We present a new methodology to quantify the total environmental impact of system design decisions. Our approach uses the thermodynamic metric of exergy consumption, adapted and validated for use by system architects. Using this methodology, we evaluate the lifecycle impact of several example system designs with environment-friendly optimizations. Our results show that environmental impact from production can be important (around 20% on current servers and growing) and system design choices can reduce this component (by 30--40%). Our results also highlight several, sometimes unexpected, cross-interactions between the environmental impact of production and operation that further motivate a total lifecycle emphasis for future green server designs.

We argue that socio-technical systems can be understood as complex adaptive systems, that is, systems containing component sub-systems interacting such that they co-evolve This viewpoint may allow us to understand more clearly the factors that underlie the complexities of socio-technical systems, and allows for a new approach to systems design predicated on unpredictable adaptive processes. System designers, we argue, need to seek to understand the underlying structures, drivers and nature of change within the system and of the system as a whole. This paper presents an outline of the complexity mechanisms that operate within socio-technical systems, and illustrates the concepts and system design implications by way of a case.

Medical schools are increasingly using curriculum information systems to better manage their curricula, to incorporate alternative learning environments, to expand subject-specific instruction, or to adapt the curricula to the changing health care environment. A curriculum information system contains key features, selected by the system's designers, that describe the objectives, the specific content, and/or the educational activities that compose the curriculum. The underlying purpose of such a system is to document and describe the knowledge, behaviors, skills, attitudes, or activities students will be expected to develop or learn. While it might be ideal to have one system that would meet the needs of all possible users, the programming and maintenance requirements of such a single system would exceed most medical schools' resources. Thus, designers of curriculum information systems must first identify the primary intended-user group: students, faculty, or administrators. The system designed for one group will typically differ from the systems for other groups in the emphasis on and level of content detail and curriculum structure information. The general structure and purposes of curriculum information systems are expressed in three distinct system designs: a curriculum database (most helpful for administrators), a curriculum textbase (for faculty), and an electronic syllabus (for students). The authors describe these different designs, and they discuss challenges faced by system designers.