Erasing by Hot Hole Injection in eSTM™ device: comprehension and optimization

The impact of nitridation on hot hole injection and the induced degradation is quantitatively studied by comparing the behavior of a control oxide and oxynitrides. The oxynitride is prepared by either annealing the oxide in N/sub 2/O or growing directly in N/sub 2/O. The pMOSFET's are uniformly stressed by using the substrate hot hole injection technique. The physical quantities analyzed include the hole injection current, the density of created interface states and the density of trapped holes. It is found that a 30 min annealing in N/sub 2/O at 950/spl deg/C can enhance the effective barrier for hole injection by 0.6 eV. However, the interface state generation during the injection is insensitive to nitridation. The continuing degradation post the hole injection is also investigated. This includes a poststress interface state build-up and the generation of new precursors for interface states. The nitridation reduces the poststress degradation considerably. Where it is necessary, the hole induced degradation is compared with that induced by electrons. The applicability of the models proposed for oxynitrides to the present results is examined.

This study compares the effects of n-channel double-gate FinFETs with fin widths $(W_{\rm fin} ) $ of 10 and 25 nm with those of such devices with back biases and hot carrier injection (HCI. Compared with the device with a wide $W_{\rm fin}$ , the device with a narrow $W_{\rm fin} $ exhibits a larger current tuning range but a more off-state current leakage at a positive back bias because of the forward-biased p-n junction and the higher degradation under HCI. The gate-induced drain leakage significantly deteriorates with a positive back bias after HCI because of the generation of interfacial charges. However, a negative back bias causing hot hole injection during HCI can alleviate the degradation compared with unbiased and positive-biased devices.

Electrical parameters degradations of silicon-on-insulator (SOI) lateral insulated-gate bipolar transistor (LIGBT) under repetitive electrostatic discharge (ESD) stresses have been investigated. After the repetitive ESD stresses, the degradation of threshold voltage (V th ) can be neglected due to the intact channel region. The decrease of on-resistance (R on ) is dominated by hot holes injection into the field oxide at the bird’s beak. Moreover, the saturation current (I ce,sat ) is decreased dramatically because of hot holes injection and interface states generation at the poly-gate edge. Finally, a novel structure with an additional P-type region beneath the poly-gate edge has been proposed to suppress the device degradation under repetitive ESD stresses.

We report on the different behaviours of interface trap generation caused by Fowler-Nordheim (F-N) electron injection and by hot-hole injection using the direct current current-voltage (DCIV) method. The hole-electron ratio of the gate current under hot-hole injection conditions is quantified. The study shows that the efficiency of hole-induced interface trap generation is about 150 times that of electron-induced interface trap generation. Furthermore, interface trap generation by both hole and electron injections obey a power-law relation with injected fluence. The hot-hole injection is observed to have a smaller power exponent than F-N electron injection.

Channel distribution of generated interface states in 0.35 μm LDD nMOSFET

We propose a novel 4-bit self-aligned SONOS-type nonvolatile memory (NVM) cell with a T-gate and I-shaped FinFET structure for practical implementation with high storage density and better reliability. In order to obtain enhanced reliability characteristics, a modified Fowler-Nordheim tunneling mechanism is employed for programming along the channel length direction, while a band-to-band hot hole injection is used for erasing along the channel width direction. With separated paths for program and erase, improved device performance is obtained with sensing margin. In order to improve the immunity to second-bit effects, the gate-induced drain leakage current method, which is a charge detection method and highly sensitive to the locally stored charges, is employed for the reading of the stored data. In terms of the scalability, we confirmed by 2-D technology computer-aided design simulation that the proposed NVM cell with channel length <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> = 50 nm operates with enough sensing margin and high-density ( ~ 5 F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit) NVM by the crossed cell array architecture.

Characterizing damage to ONO dielectrics induced during programming SONOS/NROM TM non-volatile semiconductor memory (NVSM) devices

In this work, the reliability degradation of a 650 V-class superjunction (SJ) MOSFET under continuous violent OFF-state avalanche-breakdown stress is studied. Decreased threshold voltage and increasing saturation current have been observed which are attributed to the injection of hot holes below the trench bottom into the gate oxide layer. High-energy electrons and holes are generated under OFF-state avalanche stress leading to accelerated and violent collision ionization. The body diode suffers from severe avalanche breakdown leading to heat generation by collision ionization. In addition, the injection of hot holes is further enhanced with the assistance of the electrical field at the bottom of the gate. These phenomena are further analyzed by experimental characterizations and theoretical simulation using TCAD tools. Our comprehensive study on the reliability degradation behaviors of SJ devices under OFF-state avalanche-breakdown stress can be instructive in future device optimization and failure analysis.

In recent field‐emission experiments a high energy tail in the field‐emitted electron distribution has been observed. It has been described as the products of a cascade process initiated by the injection of hot holes into the conduction band. Another process that can possibly contribute to the tail current is multiple particle tunneling. In the present development we consider the features of this tunneling process. We observe from the data that an infrared divergence‐like behavior occurs in the tail current at the Fermi energy. We argue that one reason for the occurrence of such a divergence is the singular transient response of the Fermi sea to the sudden establishment of a hole potential when an electron near the Fermi energy tunnels.

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n/sup -/ doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n/sup +/ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n/sup -/ doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The gate oxide region affected by injected hot electrons and/or holes along the channel is experimentally determined. The oxide region varies with bias conditions, and the device degradation rate is correlated with the change in the hot-carrier injected region. Based on these results, the following degradation mechanism is proposed: 1) The degradations in transconductance, threshold voltage, and subthreshold slope can be caused mainly by trapped electrons, but not generated interface states. 2) Enhanced degradation due to both hot-electron and hole injections is caused by electrons trapped in neutral centers produced by hot-hole injection.

A novel programming by hot-hole injection nitride electron storage (PHINES) Flash memory technology is developed. The memory bit size of 0.046 /spl mu/m/sup 2/ is fabricated based on 0.13-/spl mu/m technology. PHINES cell uses a nitride trapping storage cell structure. Fowler-Nordheim (FN) injection is performed to raise V/sub t/ in erase while programming is done by lowering a local V/sub t/ through band-to-band tunneling-induced hot hole (BTBT HH) injection. Two-bits-per-cell feasibility, low-power and high-speed program/erase, good endurance and data retentivity make it a promising candidate for Flash EEPROM technology in gigabit era applications.

The pursuit of non-volatile memory with program speeds below one nanosecond, beyond the capabilities of non-volatile flash and high-speed volatile static random-access memory, remains a longstanding challenge in the field of memory technology1. Utilizing fundamental physics innovation enabled by advanced materials, series of emerging memories2, 3, 4–5 are being developed to overcome the speed bottleneck of non-volatile memory. As the most extensively applied non-volatile memory, the speed of flash is limited by the low efficiency of the electric-field-assisted program, with reported speeds6, 7, 8, 9–10 much slower than sub-one nanosecond. Here we report a two-dimensional Dirac graphene-channel flash memory based on a two-dimensional-enhanced hot-carrier-injection mechanism, supporting both electron and hole injection. The Dirac channel flash shows a program speed of 400 picoseconds, non-volatile storage and robust endurance over 5.5 × 106 cycles. Our results confirm that the thin-body channel can optimize the horizontal electric-field (Ey) distribution, and the improved Ey-assisted program efficiency increases the injection current to 60.4 pA μm−1 at |VDS| = 3.7 V. We also find that the two-dimensional semiconductor tungsten diselenide has two-dimensional-enhanced hot-hole injection, but with different injection behaviour. This work demonstrates that the speed of non-volatile flash memory can exceed that of the fastest volatile static random-access memory with the same channel length.

New experiments for the deuterium isotope effect for hot hole and electron injection have been performed to probe the mechanism for the interface trap generation in n-MOS transistors. The results from these new experiments suggest that electrons in the channel, but not those electrons or holes injected into the oxide, are primarily responsible for the interface trap generation. The bond breaking at the SiO/sub 2/-Si interface is primarily due to the multiple vibrational excitation, which involves in a strong isotope effect.

In this work, a detailed analysis of capacitance behavior of high voltage MOSFET (HV-MOS) e.g. LDMOS, VDMOS using device simulation is made. The impact of lateral non-uniform doping and drift region is separately analyzed. It is shown that the peaks in C-GD and C-GS capacitances of HV-MOS originate from lateral non-uniform doping. The drift region decreases the C-GD capacitance and increases the peaks in CGS and also gives rise to peaks in C-GG capacitances increasing with higher drain bias. It is also shown that trapped charge due to hot carrier degradation modulates (or introduce) the peaks amplitude and position in capacitances depending on hot hole or electron injection at drain or source side. This capacitance analysis will facilitate in optimization of the HV-MOS structure and also help in modeling of HV-MOS, including the hot carrier degradation.