Erlang-k-based packet latency prediction model for optimal configuration of software routers

As applications scale to increasingly large processor counts, the interconnection network is frequently the limiting factor in application performance. In order to achieve application scalability, the interconnect must maintain high bandwidth while minimizing variation in packet latency. As the offered load in the network increases with growing problem sizes and processor counts, so does the expected maximum packet latency in the network, directly impacting performance of applications with any synchronized communication. Age-based packet arbitration reduces the variance in packet latency as well as average latency. This paper describes the Cray XT router packet aging algorithm which allows globally fair arbitration by incorporating age in the packet output arbitration. We describe the parameters of the aging algorithm and how to arrive at appropriate settings. We show that an efficient aging algorithm reduces both the average packet latency and the variance in packet latency on communication-intensive benchmarks.

HPC systems have shifted to burst buffer storage and high radix interconnect topologies in order to meet the challenges of large-scale, data-intensive scientific computing. Both of these technologies have been studied in detail independently, but the interaction between them is not well understood. I/O traffic and communication traffic from concurrently scheduled applications may interfere with each other in unexpected ways, and this behavior may vary considerably depending on resource allocation, scheduling, and routing policies.In this work, we analyze I/O and network traffic interference on burst-buffer-equipped dragonfly-based systems using the high-resolution packet-level simulations provided by the CODES storage and interconnect simulation framework. The analysis is performed using realistic I/O workload sizes, a variety of resource allocation and network routing strategies employed in production environments, and a dragonfly network configuration modeled after current vendor options. We analyze the impact of interference on both I/O and communication traffic.We observe that although average network packet latency is stable across a wide variety of configurations, the maximum network packet latency in the presence of concurrent I/O traffic is highly sensitive to subtle policy changes. Our simulations reveal a worst-case single packet latency of 4,700 times the average latency for sub-optimal configurations. While a topology-aware mapping of compute nodes to burst buffer storage nodes can minimize the variation in maximum packet latency, it can slow down the I/O traffic by creating contention on the burst buffer nodes. Overall, balancing I/O and network performance requires careful selection of routing, data placement, and job placement policies.

Many different factors, such as topology, routing technique, selection function, flow control policy, complexity of router design, contribute to the performance of networks on chip (NoCs). Among these factors, the choice of topology and routing function has a significant effect on the average packet latency and saturation behavior. Torus is popular in many application domains, while the problem of virtual channel misbalance caused by its deadlock avoidance scheme brings lots of performance pathologies. In this paper, we present a novel deadlock avoidance scheme based on draining scheme, and propose a deadlock-free routing scheme for torus networks. We quantify the effects of the proposed routing scheme on the overall network performance by presenting simulation results for 1-D torus and 2-D torus NoCs. Experimental results show that the novel routing algorithm for torus networks could make more efficient use of virtual channel resources, and hence cutting down packet latency and boosting throughput. Note although this paper has considered 1-D and 2-D torus networks in the experimental evaluation, the new scheme is flexible enough to support highradix torus networks.

All optical path interconnection networks employing dense wavelength division multiplexing can provide vast improvements in supercomputer performance. However, the lack of efficient optical buffering requires investigation of new topologies and routing techniques. This paper introduces and evaluates the data vortex optical switching architecture which uses cylindrical routing paths as a packet buffering alternative. In addition, the impact of the number of angles on the overall network performance is studied through simulation. Using optimal topology configurations, the data vortex is compared to two existing switching architectures-butterfly and omega networks. The three networks are compared in terms of throughput, accepted traffic ratio, and average packet latency. The data vortex is shown to exhibit comparable latency and a higher acceptance rate (2times at 50 percent load) than the butterfly and omega topologies

Modern commodity hardware architectures, with their multiple multi-core CPUs and high-speed system interconnects, exhibit tremendous power. In this paper, we study performance limitations when building both software routers and software virtual routers on such systems. We show that the fundamental performance bottleneck is currently the memory system, and that through careful mapping of tasks to CPU cores, we can achieve forwarding rates of 7 million minimum-sized packets per second on mid-range server-class systems, thus demonstrating the viability of software routers. We also find that current virtualisation systems, when used to provide forwarding engine virtualisation, yield aggregate performance equivalent to that of a single software router, a tenfold improvement on current virtual router platform performance. Finally, we identify principles for the construction of high-performance software router systems on commodity hardware, including full router virtualisation support.

A new geometric error modeling approach for multi-axis system based on stream of variation theory

The Third Generation Partnership Project (3GPP) has specified Cellular Vehicle-to-Everything (C-V2X) radio access technology in Releases 15–17, with an emphasis on facilitating direct communication between vehicles through the interface, sidelink PC5. This interface provides end-to-end network slicing functionality together with a stable cloud-native core network. The performance of direct vehicle-to-vehicle (V2V) communications has been improved by using the sidelink interface, which allows for a network infrastructure bypass. Sidelink transmissions make use of orthogonal resources that are either centrally allocated (Mode 1, Release 14) or chosen by the vehicles themselves (Mode 2, Release 14). With growing interest in connected and autonomous vehicles, the advancement in radio access technologies that facilitate dependable and low-latency vehicular communications is becoming more significant. This is especially necessary when there are heavy traffic conditions and patterns. We thoroughly examined the New Radio (NR) sidelink’s performance based on 3GPP Releases 15–17 under various vehicle densities, speeds, and distance settings. Thus, by evaluating sidelink’s strengths and drawbacks, we are able to optimize resource allocation to obtain maximum coverage in urban areas. The performance evaluation was conducted on Network Simulator 3 (NS3.34/5G-LENA) utilizing various network metrics such as average packet reception rate, throughput, and latency.

IP video surveillance (IPVS) systems, unlike traditional analog-based systems, are capable of operating over pre-existing computer networks. As a consequence, resource contention among the video streams from multiple IP cameras and traffic from other applications can significantly degrade the overall performance of the underlying network. Software Defined Networking (SDN) is a relatively new paradigm which aims to build programmable and flexible networks. By separating forwarding and control functions, the centralized SDN controller can create a map of the network topology by relying on the information provided by the switches. This paper proposes an SDN-based framework to enhance the performance of IPVS systems deployed over underprovisioned networks. In order to assist the controller's rerouting and bitrate adjustment decisions, a video quality indicator was also formulated by using the FlowStats messages queried from the switches via OpenFlow, a widely recognized protocol in SDN. Moreover, our framework is designed based on the observation that the video streams in surveillance systems offer varying utilities depending on the captured event. Experimental results show that employing the proposed solution reduced the video streams' average packet loss, latency and jitter by 87%, 11%, 7%, respectively and also increased throughput by 8%. Furthermore, the comparison of the video streams' QoS metrics suggests that the proposed solution can prioritize the reception of selected streams.

Wearable sensors combined with machine learning (ML) offer a promising approach for estimating joint kinetics in real-world settings, with potential applications in athlete monitoring and injury prevention. However, the variety of sensor configurations in previous studies complicates comparisons and optimal configuration selection. This study compared different wearable sensor configurations, comprising inertial measurement units (IMUs) and pressure insoles (PIs), to determine their influence on the accuracy of ML – based predictions of 3D knee moments during running. Sensor configurations ranged from one to four IMUs, with and without PIs. The dataset consisted of wearable and ground truth knee moment data from 19 recreational runners during treadmill running. Model performance of the convolutional neural networks was evaluated on an independent test set. Hyperparameter optimization (HPO) was applied to refine model architectures and training parameters. Performance gains by PIs and a greater number of IMUs were small but significant. The results after HPO confirmed similar performances between single- and multi-sensor configurations, suggesting only small benefits from additional sensors. Our findings highlight that both sensor configuration and model optimization play critical roles in achieving optimal performance. We provide practical recommendations for sensor selection, balancing accuracy and feasibility, to enable biomechanical assessments in real-world environments.

Efficient implementation of globally-aware network flow control

S-Mesh: a Mesh-based on-chip network with separation of control and transmission

Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture where a few application-specific long-range links are inserted on top of a regular mesh network. This way, we can better exploit the benefits of both complete regularity and partial customization. Indeed, our experimental results show that inserting application-specific long-range links significantly increases the critical traffic workload at which the network state transits from a free to a congested regime. This, in turn, results in a significant reduction in the average packet latency and a major improvement in the network achievable throughput.

Data Centers (DCs) are experiencing a tremendous growth in the number of hosted servers. Aggregate bandwidth requirement is a major bottleneck to data center performance. New Data Center Network (DCN) architectures are proposed to handle different challenges faced by current DCN architecture. In this paper we have implemented and simulated two promising DCN architectural models, namely switch-based and hybrid models, and compared their effectiveness by monitoring the network throughputs and average packet latencies. The presented analysis may be a background for the further studies on the simulation and implementation of the DCN customized topologies, and customized addressing protocols in the large-scale data centers.

Prompt and reliable communication between vehicular nodes are essential as its limited coverage and dynamic mobility rate introduces frequent change of network topology. The key feature of vehicular communication that establishes direct connectivity or Road Side Unit-based data transfer among vehicular nodes is responsible for sharing emergency information during critical situations. Multicast routing data dissemination among vehicular nodes is considered to be the potential method of parallel data transfer as they facilitate the option of determining an optimal multicast tree from feasible number of multicast trees established between the source and destinations. This estimation of optimal multicast tree using meta-heuristic techniques is confirmed to improve the throughput and reliability of the network when QoS-based constraints are imposed during multicast routing. An Improved Shuffled Frog-Leaping Algorithm-Based QoS Constrained Multicast Routing (ISFLABMR) is proposed for estimating an optimal multicast tree that confirms effective multi-constrained applied multicast routing between vehicular nodes. ISFLABMR minimizes the cost of transmission to 22% by reducing the number of multicast clusters formed during multicasting through the utilization of local and global-based optimizations. The simulation results of ISFLABMR proveits predominant reduction rate of 24% and 21% in average packet latency and energy consumptions incurred under multicast routing.

This paper introduces a deep reinforcement learning approach for optimizing network-on-chip layout verification and route optimization. The proposed method addresses the challenges of increasing design complexity and traditional verification limitations in modern VLSI circuits. A novel three-headed policy gradient network architecture is developed to handle layout verification and routing optimization tasks simultaneously. The framework integrates feature extraction networks for topology analysis, policy networks for decision-making, and value networks for performance evaluation. The system employs a complex-valued reinforcement learning model to capture both spatial and temporal dependencies in NoC designs. Experimental results demonstrate significant improvements across multiple performance metrics: a 23.4% reduction in average packet latency, a 23.6% increase in network throughput, and a 20.8% decrease in power consumption compared to conventional methods. The verification accuracy achieves 98.7% with a false positive rate below 0.5%. The framework maintains consistent performance across various network sizes and traffic patterns, demonstrating robust scalability and practical applicability in real-world chip designs. Implementation results on ISPD 2005 benchmarks validate the effectiveness of the proposed approach, showing superior performance in both verification accuracy and optimization efficiency compared to existing state-of-the-art methods.