Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems

An important practical problem in fault diagnosis is discriminating between permanent faults and transient faults. In many computer systems, the majority of errors are due to transient faults. Many heuristic methods have been used for discriminating between transient and permanent faults; however, we have found no previous work stating this decision problem in clear probabilistic terms. We present an optimal procedure for discriminating between transient and permanent faults, based on applying Bayesian inference to the observed events (correct and erroneous results). We describe how the assessed probability that a module is permanently faulty must vary with observed symptoms. We describe and demonstrate our proposed method on a simple application problem, building the appropriate equations and showing numerical examples. The method can be implemented as a run-time diagnosis algorithm at little computational cost; it can also be used to evaluate any heuristic diagnostic procedure by comparison.

The double circuit EHV transmission lines have been widely used because of its many advantages. But when faults occur, the style of fault and the operation condition are more complicated than that on the single circuit transmission line. The faults occurred on the transmission lines is mainly transient fault. The auto-reclosure is normally applied after the fault line tripped to improve the power supplies reliability and the power system safety. But if the fault is permanent and the auto-reclosure reclosed accordingly, the power system and its apparatus will suffer short circuit current again, resulting further damage of the equipment and making power system instability. Thus, it is very important to distinguish the transient and permanent fault before the tripped fault line auto-reclose. If the EHV line has shunt reactor, identification of fault nature becomes even more difficult. There are several methods proposed for distinguishing the transient and permanent fault but mainly for single circuit transmission line. In this paper, a novel method is proposed for the EHV double circuit transmission lines with shunt reactor. After tripped, the phase voltage across shunt reactor was calculated using our established transient fault line model regardless of the fault is transient or permanent. The difference between the calculated voltage and the measured voltage of the fault phase across shunt reactor was employed to identify transient or permanent fault. The amplitude ratio, i.e. the difference of the voltage between calculated and measured to the voltage across neutral reactor was used to judge fault nature. If the amplitude ratio is greater less than 1, the fault is regarded as transient. If it is more than 1, it is regarded as permanent. This result can be further verified by EMTP simulation.

CMOS scaling has greatly increased concerns for both lifetime reliability due to permanent faults and soft-error reliability due to transient faults. Most existing works only focus on one of the two reliability concerns, but often times techniques used to increase one type of reliability may adversely impact the other type. A few efforts do consider both types of reliability together and use two different metrics to quantify the two types of reliability. However, for many systems, the user's concern is to maximize system availability by improving the mean time to failure (MTTF), regardless of whether the failure is caused by permanent or transient faults. Addressing this concern requires a uniform metric to measure the effect due to both types of faults. This paper introduces a novel analytical expression for calculating the MTTF due to transient faults. Using this new formula and an existing method to evaluate system MTTF, we tackle the problem of maximizing availability for multicore real-time systems with consideration of permanent and transient faults. A framework is proposed to solve the system availability maximization problem. Experimental results on a hardware board and simulation results of synthetic tasks show that our scheme significantly improves system MTTF (and hence availability) compared with existing techniques.

CMOS scaling has greatly increased concerns for lifetime reliability due to permanent faults and soft-error reliability due to transient faults. Most existing works only focus on one of the two reliability concerns, but often times techniques used to increase one type of reliability may adversely impact the other type. A few efforts do consider both types of reliability together and use two different metrics to quantify the two types of reliability. However, for many systems, the concern of the user is to maximize system availability by improving the mean time to failure (MTTF), regardless of whether the failure is caused by permanent faults or transient faults. Addressing this concern requires a uniform metric to measure the effect due to both types of faults. In this paper, we derive a novel analytical expression for calculating the MTTF due to transient faults. Using this new formula and an existing method to evaluate system MTTF, we formulate and solve the problem of maximizing system availability with consideration of permanent faults, transient faults, and throughput constraint. Extensive simulations of synthetic task sets and benchmarks based on real-world applications were performed to validate our algorithm.

Discrimination between transient fault and permanent fault is contemporary problems for protection of transmission line. Auto‐reclosure is one of the foremost solutions for the same. This study presents the development of auto‐reclosure scheme using modified full‐cycle discrete Fourier transform with adaptive dead time control. The discrimination between transient and permanent fault is done using differential voltage across the contacts of circuit breaker. Reclosing instance is identified by comparing absolute value of positive sequence voltage, phase difference and frequency difference with a respective preset threshold using synchronism check relay. The proposed scheme has been validated by simulating power system considering variation in fault location, fault clearance angle, fault resistance and load flow in PSCAD/EMTDC. The algorithm for the auto reclosing scheme is validated in MATLAB software. Real time emulation of the proposed algorithm is performed using AVR ATmega 328P controller on laboratory prototype. The test results of simulation and hardware emulation corroborate the efficacy of the proposed technique.

This work investigates an improved protection solution based on the use of artificial neural network on the 330 kV Nigerian network modeled using MATLAB R2014a. Measured fault voltages and currents signals decomposed using the discrete Fourier transform implemented via fast Fourier transform are fed as inputs to the neural network. The output plots of the neural network shows its successful application to fault diagnosis (fault detection, fault classification and fault location). Unlike conventional protection schemes, the neural network can be adapted to distances which can cover the entire length of the protected line. Numerical assessment carried out on the neural network fault locator shows a reduced time of operation of 5.15 ms as compared to the 0.350 s with the use of ordinary numerical relays. This work also investigates the adaptive auto-reclosure scheme implemented using artificial neural network. The adaptive reclosure scheme has been adapted for use in the Nigerian network successfully to distinguish transient and permanent faults. Simulation results prove that the adaptive reclosure scheme was able to detect a line-to-ground transient fault and clear this fault in 0.1 s while the line-to-ground permanent fault is cleared after 0.14 s. The fault diagnostic algorithm designed using artificial neural network (ANN) for the 330 kV network was tested on a 132 kV network. Results show and prove that the algorithm is flexible and can be adopted to other networks.

Semiconductor technology scaling makes chips moresensitive to faults. This paper describes the DeSyRe designapproach and its runtime management for future reliable embedded Multiprocessor Systems-on-Chip (MPSoCs). A light weight runtime system is described for shared-memory MPSoCs to support fault-tolerant execution upon detection of transient and permanent faults. The DeSyRe runtime system offers re-execution of tasks that suffer from transient faults and task-migration in cases where a worker processor is permanently faulty. In addition, a faulty worker can potentially remainusable, increasing systems fault-tolerance. This is achieved using alternative task implementations, which avoid the faulty circuit and are indicated in the application-code via pragma annotations, as well as by repairing a faulty core via hardware reconfiguration. Thereby, the system can be dynamically adapted using one ormultiple of the above mechanisms to mitigate faults. The DeSyReruntime system is evaluated using micro-benchmarks running ona Virtex-6 FPGA MPSoC. Results suggest that our enhance dfault-tolerant runtime system can successfully and efficiently execute all application tasks under a variety of fault cases.

FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuit's operation. We present a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CEO) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques.

A novel nonfault detection method using fault location to calculate the differential currents at fault point is proposed for three-phase reclosure in transmission lines with shunt reactors. In the case of a transient fault with the extinction arc namely nonfault, the differential currents of three-phase at fault point are all zeros. But in the case of an arcing transient fault or a permanent fault, the differential currents in the fault phases are non-zero because of the fault branch, and the differential currents of the healthy phases are close to zero as that of an arc extinction transient fault. Meanwhile, the fault phase can be confirmed as well based on the differential currents in the fault phases. It is noted that the presented non-fault detection is independent on fault phase selection and is able to detect non-fault reliably before three-phase reclosing, which is helpful to avoid blind reclosing and identify the fault phase for the arcing faults especially serious permanent faults. Moreover, simulations verify the correctness and effectiveness of this non-fault detection method, which is helpful to improve successful reclosing rate for three-phase reclosure.

Increasing complexity of safety-critical systems that support real-time multitasking applications requests the concurrency management offered by real-time operating systems (RTOS). Real-time systems can suffer severe consequences if the functional as well as the time specifications are not met. In addition, real-time systems are subject to transient errors originating from several sources, including the impact of high energy particles on sensitive areas of integrated circuits. Therefore, the evaluation of the sensitivity of RTOS to transient faults is a major issue. This paper explores sensitivity of RTOS kernels in safety-critical systems. We characterize and analyze the consequences of transient faults on key components of the kernel of MicroC, a popular RTOS. We specifically focus on its task scheduling and context switching modules. Classes of fault syndromes specific to safety-critical real-time systems are identified. Results reported in this paper demonstrate that 34% of faults that affect the scheduling and context switching functions led to scheduling dysfunctions. This represents an important fraction of faults that cannot be ignored during the design phase of safety-critical applications running under an RTOS

Onboard computers use redundant hardware for fault tolerance resulting in underutilisation of resources under fault free condition. This paper exploits the resource augmented model where task allocation based on task criticality ensures safe minimal functionality under permanent fault. An algorithm has been designed for real-time scheduling with fault tolerance and precedence constraints for hot standby dual redundant navigation, guidance, and control system. This algorithm is designed for recovery under permanent hardware fault in different case studies of single, double and triple units of different types (N, G, and C). It can tolerate permanent software failures, transient hardware and software failures occurring singly or as a combination in same type unit. Tolerating increased frequency of transient and software faults with same allowable safety margins and an increased flexibility in enhanced operational performance by different operational modes under fault and fault free condition without degrading safety margins are significant performance aspects of this design.

FPGAs are widely used for prototyping of digital systems. A major problem of current FPGA architectures is that if there is a fault in a single combinational logic block (CLB), it may take a significant amount of time to find an alternative mapping of the circuit to bypass the faulty block. Thus, there is a need for new type of FPGA architecture that allows rapid recovery from internal faults in a FPGA. Currently only the detection of permanent faults in logic blocks, and on their interconnections are considered in FPGA-based systems. Several studies in recent years have shown that transient faults are likely to occur at a much higher rate than permanent faults in submicron VLSI devices. The only way to cope with transient faults in FPGAs is to detect them as soon as they occur, and perform on-line reconfiguration to recover from their effects. This paper presents a reconfigurable FPGA architecture that enables on-line fault detection in the constituent CLBs of the FPGA.

Proposed here is a novel architecture for a fault-tolerant real-time system. We employ a checkpoint rollback strategy with double modular redundancy. Main consideration is given to how to recover from both transient and permanent faults without any built-in fault-detection modules or spare processors. Besides state comparison between duplicated tasks, the system has access to the state of the previous checkpoint so that the integrity of a processor can be checked. Using a Markov model capturing the behavior of the proposed scheme, we calculate the probability of task completion against faults that occur in a Poisson process. The optimal number of checkpoints is selected so as to maximize the probability of task completion.

The VLSI based circuits often pose challenges in the form of various faults (such as transient faults, permanent faults, stuck-at-faults). These faults appear even after testing also. They occur because of reduction in the size of the circuit or during realtime implementation, as these faults are difficult to detect. It is very important to detect and rectify all such faults to make the system foolproof and achieve expected functionality. In this paper, 12 transistors based, full adder circuit (12T-FAC) using Carbon Nanotube Field Effect Transistor (CNFET) technology is proposed. The proposed design based on CNFET provides high fault resistance towards transient, permanent faults and works with least power, delay and power-delay product (PDP). Later, features like fault detection and correction circuit have been added in 12T-FAC. The final version of full adder circuit capable of correcting errors has been used in designing applications like multipliers. The proposed full adder circuit was designed with CNFET technology, simulated at 32 nm with supply voltage +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM.

The process of repairing Web Service failures may be connected to the nature of the fault that caused the error generating the failure. The selection strategy for composed services repair may be drawn from an analysis on temporal behavior of the fault, assessing if fault is transient, intermittent or permanent. The repair process strictly depends on the permanence type of faults, as substitution is applied with permanent faults, while retry is chosen with transient faults and the retry period is to be determined. In this paper we propose a methodology and a tool for learning the repair strategies of Web Services to automatically select repair actions. This methodology is able to incrementally learn its knowledge of repairs, as faults are repaired. Thus, it is at runtime possible to achieve adaptability according to the current fault features and to the history of the previously performed repair actions. This learning technique and the strategy selection are based on a Bayesian classification of faults in permanent, intermittent and transient, followed by a comparative analysis between current fault features and previously classified faults features which suggests which repair strategy has to be applied. Therefore, this methodology includes the ability to learn autonomously both model parameters, which are useful to determine the fault type, and repair strategies which are successful and proper for a particular fault.