Error Detection Schemes for CED in Block Ciphers

Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Berger code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents a concurrent error detection (CED) scheme for orthogonal Latin square (OLS) parallel decoders. Different from a CED scheme found in the technical literature that protects only the syndrome generator, the proposed CED scheme protects the whole OLS decoder for single stuck-at faults. This paper presents the detailed design and analysis of the proposed CED scheme and shows that it is strongly fault secured for single stuck-at faults. Extensive simulation results are also provided; different figures of merit such as area, power dissipation, gate depth, and coverage are assessed. It is shown that the proposed decoder designs for ( n, k) t-bit error correcting OLS codes (k = 16 ...256; t = 2 ...5) have reasonable overhead; for example, the average area overhead of the proposed CED is 35.5 (23.6) % compared with an OLS decoder with no CED (i.e., the previously reported CED scheme). However, the most significant advantage of the proposed scheme is that it achieves 100% fault coverage for the whole CED circuit, thus providing a very efficient and fully fault-tolerant implementation. The proposed CED is applicable to both binary and nonbinary OLS codes; the CED for a nonbinary OLS decoder achieves comparable or better results than a binary OLS decoder. Moreover, simulation shows that the proposed CED scheme is better than double modular redundancy.

With the increasing chip density and the continuous improvement of reliability requirements, the concurrent error detection techniques in register transfer level have become an increasing concern. Because of the actual low probability of failure occurring, a number of semi-concurrent error detection techniques are feasible. The circuits can be checked in every N iterations. So the recomputations will have N-1 free iterations. This paper can take full advantage of the free iterations to achieve the concurrent processing of the original computation, thus enhancing performance. The proposed strategy is actually independent from a specific scheduling-and-allocation algorithm; however, for recomputations the conventional duplication with comparison leads to high circuit complexity increase. So we modify the force-directed algorithm to ease the hardware overhead as well as to ensure that the data path is fault-secure in an iteration.

We present a Concurrent Error Detection (CED) scheme for the Scheduler of a modern microprocessor. The proposed CED scheme is based on monitoring a set of invariances imposed through added hardware, violation of which signifies the occurrence of an error. The novelty of our solution stems from the workload-cognizant way in which these invariances are selected so that they leverage the application-level error masking inherent in program execution. Specifically, in order to ensure cost-effectiveness of the hardware employed to construct these invariances, we make use of information regarding the type and frequency of errors affecting the typical workload of the microprocessor. Thereby, we identify the most susceptible aspects of instruction execution and we accordingly distribute CED resources to protect them. Our approach is demonstrated on the Scheduler of an Alpha-like superscalar microprocessor with dynamic scheduling, hybrid branch prediction and out-of-order execution capabilities. Using an extensive fault-simulation infrastructure that we developed around this microprocessor, we profile the impact of Scheduler faults across a variety of different SPEC2000 benchmarks. Based on the results, we construct a CED scheme which monitors the time and location of instruction execution, the executed operation, the utilized resources, as well as the executed and retired sequence of instructions. At a hardware cost of only 32 percent of the Scheduler, the corresponding CED scheme detects over 85 percent of its faults that affect the architectural state of the microprocessor. Furthermore, over 99.5 percent of these faults are detected before they corrupt the architectural state, while the average detection latency for the remaining faults is in the order of a few clock cycles, implying that efficient recovery methods can be developed.

Concurrent Error Detection (CED) methods are commonly employed to provide some level of error detection capability at the cost of some area and power overhead. In many applications, however, the error detection capability must be reconfigured dynamically, in order to adapt to the available power budget, criticality of the processed data, a thermal-safe schedule, etc. In this work, we propose a reconfigurable duplication-based CED infrastructure for logic circuits. The key idea is to enable/disable the operation of the duplicate circuit according to a set of control conditions. When CED is disabled, the inputs to the duplicate circuit retain their previous values (i.e., reduction in power dissipation via elimination of switching activity), yet errors are not detected (i.e., reduction in CED coverage). Experimental results using judicious and random selection of control conditions yield the same end-result; power dissipation is commensurate with CED coverage. Therefore, LFSR structures can be used to easily generate and reconfigure conditions, enabling their dynamic adjustment to adapt to the power constraints of the system.

In this paper we propose two algorithm-level time redundancy based Concurrent Error Detection (CED) schemes that exploit diversity in a Register Transfer (RT) level implementation. RT level diversity can be achieved either by changing the operation-to-operator allocation (allocation diversity) or by shifting the operands before re-computation (data diversity). By enabling a fault to affect the normal result and the re-computed result in two different ways, RT level diversity yields good CED capability with low area overhead. We used Synopsys Behavior Compiler (BC) to implement the technique.

Galois-field (GF) is a number system with a finite set of elements. It is widely used in error-control coding, cryptography, etc. Among its important arithmetic operations, inversion and division have been identified as the most complicated. In this paper, concurrent error detection (CED) schemes have been presented for a systolic GF(2/sup m/) inverter that we have proposed recently. The CED circuitry tests the inverter concurrently while it is in normal operation to increase the reliability of the inverter. There is negligible performance penalty. Analysis shows that all single cell faults can be detected concurrently. The area overhead is less than 5% for 11 bits or longer words.

In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting soft errors into partial bitstream in FPGA by an SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, for fault tolerant architecture Markov dependability models are created and how the reliability and availability parameters derived from this model for different configurations of architectures and faulty modules is demonstrated. The reliability analysis results are then shown.

Today, encryption is widely used to incorporate privacy in data communications. Hardware implementations of encryption algorithms are fast enough to cope with the high throughput required in modern transmission channels. However, faults may occur in such circuits that can cause errors in encrypted text. A new technique is proposed to concurrently detect errors in block ciphers. It introduces very low area overhead in the system. In addition, a new encoding scheme is presented that has higher detection capabilities than other common error detection codes, when applied to encryption systems. Experiments conducted with widely used encryption algorithms (DES, RC5, IDEA and SKIPJACK) demonstrate the advantages of the proposed technique.

In this work we propose a hybrid concurrent error detection (CED) scheme that combines the implication-based method with the parity check method. The parity check method is easy to implement and has high probability of detecting errors, while the implication-based method has high flexibility to be easily integrated with other CED methods for improidng the probability of detecting errors. In addition, fault diagnosis capability can even be enabled by integrating implications. We show that by combining these two methods, not only the probability of detecting errors can be significantly increased, but also the diagnosability of the target circuit can be effectively enhanced. A systematical flow is developed to add the required checking logic of implications into the most appropriate locations in the target circuit for detecting undetected errors by the parity check method. This minimizes the total number of the employed implications and thus the incurred area overhead. The experimental results show that 89.08% of area overhead is required yet the probability of detecting errors is improved from 88.32% to 97.73% by the proposed hybrid scheme. The results also show that the achievable diagnosability of our scheme enhances from 91.79% to 96.36% on average. More than 200 equivalent faults also become distinguishable in our scheme.

Fault tolerance is of great importance for big data systems. Although several software-based application-level techniques exist for fault security in big data systems, there is a potential research space at the hardware level. Big data needs to be processed inexpensively and efficiently, for which traditional hardware architectures are, although adequate, not optimum for this purpose. In this paper, we propose a hardware-level fault tolerance scheme for big data and cloud computing that can be used with the existing software-level fault tolerance for improving the overall performance of the systems. The proposed scheme uses the concurrent error detection (CED) method to detect hardware-level faults, with the help of Scalable Error Detecting Codes (SEDC) and its checker. SEDC is an all unidirectional error detection (AUED) technique capable of detecting multiple unidirectional errors. The SEDC scheme exploits data segmentation and parallel encoding features for assigning code words. Consequently, the SEDC scheme can be scaled to any binary data length “n” with constant latency and less complexity, compared to other AUED schemes, hence making it a perfect candidate for use in big data processing hardware. We also present a novel area, delay, and power efficient, scalable fault secure checker design based on SEDC. In order to show the effectiveness of our scheme, we (1) compared the cost of hardware-based fault tolerance with an existing software-based fault tolerance technique used in HDFS and (2) compared the performance of the proposed checker in terms of area, speed, and power dissipation with the famous Berger code and m-out-of-2m code checkers. The experimental results show that (1) the proposed SEDC-based hardware-level fault tolerance scheme significantly reduces the average cost associated with software-based fault tolerance in a big data application, and (2) the proposed fault secure checker outperforms the state-of-the-art checkers in terms of area, delay, and power dissipation.

This paper presents a procedure for synthesizing multilevel circuits with concurrent error detection based on Bose-Lin codes (1985). Bose-Lin codes are an efficient solution for providing concurrent error detection as they are separable codes and have a fixed number of check bits, independent of the number of information bits. Furthermore, Bose-Lin code checkers have a simple structure as they are based on modulo operations. Procedures are described for synthesizing circuits in a way that their structure ensures that all single-point faults can only cause errors that are detected by a Bose-Lin code. This paper also presents an efficient scheme for concurrent error detection in sequential circuits. Both the state bits and the output bits are encoded with a Bose-Lin code and their checking is combined such that one checker suffices. Results indicate low area overhead. The cost of concurrent error detection is reduced significantly compared to other methods.

In reversible circuits, a fault as a change in logic value at a circuit node always alters an output logic value, so observability of faults at the output is 100%. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible circuits to design CMOS circuits having perfect or 100% Concurrent Error Detection (CED). For this purpose we propose a new, fault preservative, and reversible gate library called Even Target Mixed Polarity Multiple Control Toffoli (ET-MPMCT). By using ET-MPCT, we ensure that the parity, even or odd, is preserved at all levels including the output level unless there is a faulty node. Our design strategy has two steps for a reversible function: 1) implement the reversible functions with the ET-MPMCT library; and 2) apply reversible-to-CMOS gate conversion. In case an irreversible function needs to be synthesized then its reversible form is used followed by the two design steps. As a result, we have come up with a CMOS circuit having 100% CED. The performance of our approach is compared with other CED schemes in the literature in terms of area, detection rate, and power consumption. Simulations are done with Cadence Genus tool using TSMC $0.18 \mu \mathrm{m}$ technology. Clearly, results are in favor of our proposed technique.

In this paper, a concurrent error detection technique for priority queue managers for ATM switches is presented. A functional model for queue managers dealing with a mixture of real-time and non-real-time traffic is developed. Based on the functional model, functional errors due to physical failures in specific modules are explicitly stated. Errors in the queue managers are detected during normal operation by checking their functional invariants. Once an error is defected, the module containing the fault can be located without any extra efforts. The hardware overhead required to check the invariants is manageably small. Moreover, the time overhead is negligible.

The use of deep sub-micron technology raises a number of concerns about reliability in VLSI circuits. Shrinking geometries and reduced power supplies leave the circuits vulnerable to 'soft' and transient errors. The combination of high clock speed and large circuit area result in high power consumption and skew in clock distribution. This paper investigates the use of concurrent error detection (CED) and asynchronous design to overcome these problems. Four pipelined processor designs are compared - two synchronous, two asynchronous with one of each type using CED. Initial results indicate an area overhead of 12% in return for a fault coverage of 98.54% of all unidirectional errors. Additionally, the asynchronous CED processor has an area overhead of only 4% when compared to the synchronous non-CED design.